Lines Matching refs:state
121 struct mutex lock; /* Protect state */
122 u32 state;
224 static inline void imx8mq_mipi_csi_write(struct csi_state *state, u32 reg, u32 val)
226 writel(val, state->regs + reg);
229 static int imx8mq_mipi_csi_sw_reset(struct csi_state *state)
238 ret = reset_control_assert(state->rst);
240 dev_err(state->dev, "Failed to assert resets: %d\n", ret);
247 static void imx8mq_mipi_csi_set_params(struct csi_state *state)
249 int lanes = state->bus.num_data_lanes;
251 imx8mq_mipi_csi_write(state, CSI2RX_CFG_NUM_LANES, lanes - 1);
252 imx8mq_mipi_csi_write(state, CSI2RX_CFG_DISABLE_DATA_LANES,
254 imx8mq_mipi_csi_write(state, CSI2RX_IRQ_MASK, CSI2RX_IRQ_MASK_ALL);
261 imx8mq_mipi_csi_write(state, CSI2RX_CFG_VID_VC_IGNORE, 1);
262 imx8mq_mipi_csi_write(state, CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL,
266 static int imx8mq_mipi_csi_clk_enable(struct csi_state *state)
268 return clk_bulk_prepare_enable(CSI2_NUM_CLKS, state->clks);
271 static void imx8mq_mipi_csi_clk_disable(struct csi_state *state)
273 clk_bulk_disable_unprepare(CSI2_NUM_CLKS, state->clks);
276 static int imx8mq_mipi_csi_clk_get(struct csi_state *state)
281 state->clks[i].id = imx8mq_mipi_csi_clk_id[i];
283 return devm_clk_bulk_get(state->dev, CSI2_NUM_CLKS, state->clks);
286 static int imx8mq_mipi_csi_calc_hs_settle(struct csi_state *state,
299 fmt = v4l2_subdev_get_pad_format(&state->sd, sd_state, MIPI_CSI2_PAD_SINK);
302 link_freq = v4l2_get_link_freq(state->src_sd->ctrl_handler,
304 state->bus.num_data_lanes * 2);
306 dev_err(state->dev, "Unable to obtain link frequency: %d\n",
313 dev_dbg(state->dev, "Out-of-bound lane rate %u\n", lane_rate);
331 esc_clk_rate = clk_get_rate(state->clks[CSI2_CLK_ESC].clk);
333 dev_err(state->dev, "Could not get esc clock rate.\n");
337 dev_dbg(state->dev, "esc clk rate: %lu\n", esc_clk_rate);
346 dev_dbg(state->dev, "lane rate %u Ths_settle %u hs_settle %u\n",
352 static int imx8mq_mipi_csi_start_stream(struct csi_state *state,
358 ret = imx8mq_mipi_csi_sw_reset(state);
362 imx8mq_mipi_csi_set_params(state);
363 ret = imx8mq_mipi_csi_calc_hs_settle(state, sd_state, &hs_settle);
367 regmap_update_bits(state->phy_gpr,
368 state->phy_gpr_reg,
379 static void imx8mq_mipi_csi_stop_stream(struct csi_state *state)
381 imx8mq_mipi_csi_write(state, CSI2RX_CFG_DISABLE_DATA_LANES, 0xf);
395 struct csi_state *state = mipi_sd_to_csi2_state(sd);
400 ret = pm_runtime_resume_and_get(state->dev);
405 mutex_lock(&state->lock);
408 if (state->state & ST_SUSPENDED) {
414 ret = imx8mq_mipi_csi_start_stream(state, sd_state);
420 ret = v4l2_subdev_call(state->src_sd, video, s_stream, 1);
424 state->state |= ST_STREAMING;
426 v4l2_subdev_call(state->src_sd, video, s_stream, 0);
427 imx8mq_mipi_csi_stop_stream(state);
428 state->state &= ~ST_STREAMING;
432 mutex_unlock(&state->lock);
435 pm_runtime_put(state->dev);
571 struct csi_state *state = mipi_notifier_to_csi2_state(notifier);
572 struct media_pad *sink = &state->sd.entity.pads[MIPI_CSI2_PAD_SINK];
574 state->src_sd = sd;
584 static int imx8mq_mipi_csi_async_register(struct csi_state *state)
594 v4l2_async_subdev_nf_init(&state->notifier, &state->sd);
596 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(state->dev), 0, 0,
607 dev_err(state->dev,
614 state->bus = vep.bus.mipi_csi2;
616 dev_dbg(state->dev, "data lanes: %d flags: 0x%08x\n",
617 state->bus.num_data_lanes,
618 state->bus.flags);
620 asd = v4l2_async_nf_add_fwnode_remote(&state->notifier, ep,
629 state->notifier.ops = &imx8mq_mipi_csi_notify_ops;
631 ret = v4l2_async_nf_register(&state->notifier);
635 return v4l2_async_register_subdev(&state->sd);
650 struct csi_state *state = mipi_sd_to_csi2_state(sd);
652 mutex_lock(&state->lock);
654 if (state->state & ST_POWERED) {
655 imx8mq_mipi_csi_stop_stream(state);
656 imx8mq_mipi_csi_clk_disable(state);
657 state->state &= ~ST_POWERED;
660 mutex_unlock(&state->lock);
666 struct csi_state *state = mipi_sd_to_csi2_state(sd);
670 mutex_lock(&state->lock);
672 if (!(state->state & ST_POWERED)) {
673 state->state |= ST_POWERED;
674 ret = imx8mq_mipi_csi_clk_enable(state);
676 if (state->state & ST_STREAMING) {
678 ret = imx8mq_mipi_csi_start_stream(state, sd_state);
684 state->state &= ~ST_SUSPENDED;
687 mutex_unlock(&state->lock);
695 struct csi_state *state = mipi_sd_to_csi2_state(sd);
699 state->state |= ST_SUSPENDED;
707 struct csi_state *state = mipi_sd_to_csi2_state(sd);
709 if (!(state->state & ST_SUSPENDED))
718 struct csi_state *state = mipi_sd_to_csi2_state(sd);
723 ret = icc_set_bw(state->icc_path, 0, 0);
733 struct csi_state *state = mipi_sd_to_csi2_state(sd);
736 ret = icc_set_bw(state->icc_path, 0, state->icc_path_bw);
756 static int imx8mq_mipi_csi_subdev_init(struct csi_state *state)
758 struct v4l2_subdev *sd = &state->sd;
764 MIPI_CSI2_SUBDEV_NAME, dev_name(state->dev));
771 sd->dev = state->dev;
773 state->pads[MIPI_CSI2_PAD_SINK].flags = MEDIA_PAD_FL_SINK
775 state->pads[MIPI_CSI2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE
778 state->pads);
794 struct csi_state *state = mipi_sd_to_csi2_state(sd);
796 icc_put(state->icc_path);
802 struct csi_state *state = mipi_sd_to_csi2_state(sd);
805 state->icc_path = of_icc_get(&pdev->dev, "dram");
806 if (IS_ERR_OR_NULL(state->icc_path))
807 return PTR_ERR_OR_ZERO(state->icc_path);
809 state->icc_path_bw = MBps_to_icc(700);
814 static int imx8mq_mipi_csi_parse_dt(struct csi_state *state)
816 struct device *dev = state->dev;
817 struct device_node *np = state->dev->of_node;
823 state->rst = devm_reset_control_array_get_exclusive(dev);
824 if (IS_ERR(state->rst)) {
825 dev_err(dev, "Failed to get reset: %pe\n", state->rst);
826 return PTR_ERR(state->rst);
843 state->phy_gpr = syscon_node_to_regmap(node);
845 if (IS_ERR(state->phy_gpr)) {
846 dev_err(dev, "failed to get gpr regmap: %pe\n", state->phy_gpr);
847 return PTR_ERR(state->phy_gpr);
850 state->phy_gpr_reg = out_val[1];
851 dev_dbg(dev, "phy gpr register set to 0x%x\n", state->phy_gpr_reg);
859 struct csi_state *state;
862 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
863 if (!state)
866 state->dev = dev;
868 ret = imx8mq_mipi_csi_parse_dt(state);
875 state->regs = devm_platform_ioremap_resource(pdev, 0);
876 if (IS_ERR(state->regs))
877 return PTR_ERR(state->regs);
879 ret = imx8mq_mipi_csi_clk_get(state);
883 platform_set_drvdata(pdev, &state->sd);
885 mutex_init(&state->lock);
887 ret = imx8mq_mipi_csi_subdev_init(state);
903 ret = imx8mq_mipi_csi_async_register(state);
913 media_entity_cleanup(&state->sd.entity);
914 v4l2_subdev_cleanup(&state->sd);
915 v4l2_async_nf_unregister(&state->notifier);
916 v4l2_async_nf_cleanup(&state->notifier);
917 v4l2_async_unregister_subdev(&state->sd);
921 mutex_destroy(&state->lock);
929 struct csi_state *state = mipi_sd_to_csi2_state(sd);
931 v4l2_async_nf_unregister(&state->notifier);
932 v4l2_async_nf_cleanup(&state->notifier);
933 v4l2_async_unregister_subdev(&state->sd);
937 media_entity_cleanup(&state->sd.entity);
938 v4l2_subdev_cleanup(&state->sd);
939 mutex_destroy(&state->lock);