Lines Matching refs:val
517 u32 val)
519 writel(val, csis->regs + reg);
530 u32 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
533 val | MIPI_CSIS_CMN_CTRL_RESET);
539 u32 val, mask;
541 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
543 val |= MIPI_CSIS_CMN_CTRL_ENABLE;
545 val &= ~MIPI_CSIS_CMN_CTRL_ENABLE;
546 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val);
548 val = mipi_csis_read(csis, MIPI_CSIS_DPHY_CMN_CTRL);
549 val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE;
552 val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE);
554 mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, val);
561 u32 val;
564 val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(0));
565 val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK
582 val |= MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL;
584 val |= MIPI_CSIS_ISPCFG_FMT(csis_fmt->data_type);
585 mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(0), val);
588 val = format->width | (format->height << 16);
589 mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0), val);
647 u32 val;
649 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
650 val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK;
651 val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET;
653 val |= MIPI_CSIS_CMN_CTRL_INTER_MODE;
654 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val);
662 val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET)
665 mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0), val);
667 val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL);
668 val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
669 val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15);
670 val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK;
671 mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val);
684 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
686 val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW |