Lines Matching refs:reg
41 static u8 zr36060_read(struct zr36060 *ptr, u16 reg)
48 value = (ptr->codec->master_data->readreg(ptr->codec, reg)) & 0xff;
55 static void zr36060_write(struct zr36060 *ptr, u16 reg, u8 value)
59 zrdev_dbg(zr, "0x%02x @0x%04x\n", value, reg);
63 ptr->codec->master_data->writereg(ptr->codec, reg, value);
488 u32 reg;
508 reg = (!pol->vsync_pol ? ZR060_VPR_VS_POL : 0)
516 zr36060_write(ptr, ZR060_VPR, reg);
518 reg = 0;
525 reg |= ZR060_SR_H_SCALE2;
529 reg |= ZR060_SR_H_SCALE4;
539 reg |= ZR060_SR_V_SCALE;
542 zr36060_write(ptr, ZR060_SR, reg);
550 reg = norm->ht - 1; /* Vtotal */
551 zr36060_write(ptr, ZR060_SGR_VTOTAL_HI, (reg >> 8) & 0xff);
552 zr36060_write(ptr, ZR060_SGR_VTOTAL_LO, (reg >> 0) & 0xff);
554 reg = norm->wt - 1; /* Htotal */
555 zr36060_write(ptr, ZR060_SGR_HTOTAL_HI, (reg >> 8) & 0xff);
556 zr36060_write(ptr, ZR060_SGR_HTOTAL_LO, (reg >> 0) & 0xff);
558 reg = 6 - 1; /* VsyncSize */
559 zr36060_write(ptr, ZR060_SGR_VSYNC, reg);
561 reg = 68;
562 zr36060_write(ptr, ZR060_SGR_HSYNC, reg);
564 reg = norm->v_start - 1; /* BVstart */
565 zr36060_write(ptr, ZR060_SGR_BVSTART, reg);
567 reg += norm->ha / 2; /* BVend */
568 zr36060_write(ptr, ZR060_SGR_BVEND_HI, (reg >> 8) & 0xff);
569 zr36060_write(ptr, ZR060_SGR_BVEND_LO, (reg >> 0) & 0xff);
571 reg = norm->h_start - 1; /* BHstart */
572 zr36060_write(ptr, ZR060_SGR_BHSTART, reg);
574 reg += norm->wa; /* BHend */
575 zr36060_write(ptr, ZR060_SGR_BHEND_HI, (reg >> 8) & 0xff);
576 zr36060_write(ptr, ZR060_SGR_BHEND_LO, (reg >> 0) & 0xff);
579 reg = cap->y + norm->v_start; /* Vstart */
580 zr36060_write(ptr, ZR060_AAR_VSTART_HI, (reg >> 8) & 0xff);
581 zr36060_write(ptr, ZR060_AAR_VSTART_LO, (reg >> 0) & 0xff);
583 reg += cap->height; /* Vend */
584 zr36060_write(ptr, ZR060_AAR_VEND_HI, (reg >> 8) & 0xff);
585 zr36060_write(ptr, ZR060_AAR_VEND_LO, (reg >> 0) & 0xff);
587 reg = cap->x + norm->h_start; /* Hstart */
588 zr36060_write(ptr, ZR060_AAR_HSTART_HI, (reg >> 8) & 0xff);
589 zr36060_write(ptr, ZR060_AAR_HSTART_LO, (reg >> 0) & 0xff);
591 reg += cap->width; /* Hend */
592 zr36060_write(ptr, ZR060_AAR_HEND_HI, (reg >> 8) & 0xff);
593 zr36060_write(ptr, ZR060_AAR_HEND_LO, (reg >> 0) & 0xff);
596 reg = norm->v_start - 4; /* SVstart */
597 zr36060_write(ptr, ZR060_SWR_VSTART_HI, (reg >> 8) & 0xff);
598 zr36060_write(ptr, ZR060_SWR_VSTART_LO, (reg >> 0) & 0xff);
600 reg += norm->ha / 2 + 8; /* SVend */
601 zr36060_write(ptr, ZR060_SWR_VEND_HI, (reg >> 8) & 0xff);
602 zr36060_write(ptr, ZR060_SWR_VEND_LO, (reg >> 0) & 0xff);
604 reg = norm->h_start /*+ 64 */ - 4; /* SHstart */
605 zr36060_write(ptr, ZR060_SWR_HSTART_HI, (reg >> 8) & 0xff);
606 zr36060_write(ptr, ZR060_SWR_HSTART_LO, (reg >> 0) & 0xff);
608 reg += norm->wa + 8; /* SHend */
609 zr36060_write(ptr, ZR060_SWR_HEND_HI, (reg >> 8) & 0xff);
610 zr36060_write(ptr, ZR060_SWR_HEND_LO, (reg >> 0) & 0xff);
635 reg = ptr->max_block_vol;
636 zr36060_write(ptr, ZR060_MBCVR, reg);