Lines Matching refs:x00
59 #define MSI_DELAY_TIMER (MSI_CONTROL_REG_BASE + 0x00)
70 #define MUX_MODE_CTRL (SYSTEM_CONTROL_REG_BASE + 0x00)
72 #define rbPaMSDtvNoGpio 0x00 /*[2:0], DTV Simple mode */
78 #define rbPbMSDtvNoGpio 0x00 /*[5:3], DTV Simple mode */
98 #define IR_Init_Reg (IR_CONTROL_REG_BASE + 0x00)
106 #define rbIRlowidle 0x00
110 #define I2C_A_CTL_STATUS (I2C_A_CONTROL_REG_BASE + 0x00)
119 #define I2C_B_CTL_STATUS (I2C_B_CONTROL_REG_BASE + 0x00)
130 #define MPEG2_CTRL_A (DTV_PORTA_CONTROL_REG_BASE + 0x00)
137 #define DMA_PORTA_CHAN0_ADDR_LOW (DMA_PORTA_CONTROL_REG_BASE + 0x00)
149 #define MPEG2_CTRL_B (DTV_PORTB_CONTROL_REG_BASE + 0x00)
156 #define AES_CTRL_B (AES_PORTB_CONTROL_REG_BASE + 0x00)
160 #define DMA_PORTB_CHAN0_ADDR_LOW (DMA_PORTB_CONTROL_REG_BASE + 0x00)