Lines Matching defs:timing
307 struct cio2_csi2_timing *timing,
322 timing->clk_termen = cio2_rx_timing(CIO2_CSIRX_DLY_CNT_TERMEN_CLANE_A,
326 timing->clk_settle = cio2_rx_timing(CIO2_CSIRX_DLY_CNT_SETTLE_CLANE_A,
330 timing->dat_termen = cio2_rx_timing(CIO2_CSIRX_DLY_CNT_TERMEN_DLANE_A,
334 timing->dat_settle = cio2_rx_timing(CIO2_CSIRX_DLY_CNT_SETTLE_DLANE_A,
339 dev_dbg(dev, "freq ct value is %d\n", timing->clk_termen);
340 dev_dbg(dev, "freq cs value is %d\n", timing->clk_settle);
341 dev_dbg(dev, "freq dt value is %d\n", timing->dat_termen);
342 dev_dbg(dev, "freq ds value is %d\n", timing->dat_settle);
359 struct cio2_csi2_timing timing = { 0 };
368 r = cio2_csi2_calc_timing(cio2, q, &timing, fmt->bpp, lanes);
372 writel(timing.clk_termen, q->csi_rx_base +
374 writel(timing.clk_settle, q->csi_rx_base +
378 writel(timing.dat_termen, q->csi_rx_base +
380 writel(timing.dat_settle, q->csi_rx_base +
593 * the best timing information to get from the hardware.