Lines Matching refs:pd
128 struct dt3155_priv *pd = vb2_get_drv_priv(vq);
129 unsigned size = pd->width * pd->height;
142 struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
144 vb2_set_plane_payload(vb, 0, pd->width * pd->height);
150 struct dt3155_priv *pd = vb2_get_drv_priv(q);
151 struct vb2_buffer *vb = &pd->curr_buf->vb2_buf;
154 pd->sequence = 0;
156 iowrite32(dma_addr, pd->regs + EVEN_DMA_START);
157 iowrite32(dma_addr + pd->width, pd->regs + ODD_DMA_START);
158 iowrite32(pd->width, pd->regs + EVEN_DMA_STRIDE);
159 iowrite32(pd->width, pd->regs + ODD_DMA_STRIDE);
162 FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
165 pd->regs + CSR1);
166 wait_i2c_reg(pd->regs);
167 write_i2c_reg(pd->regs, CONFIG, pd->config);
168 write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);
169 write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);
172 write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);
178 struct dt3155_priv *pd = vb2_get_drv_priv(q);
181 spin_lock_irq(&pd->lock);
183 write_i2c_reg_nowait(pd->regs, CSR2, pd->csr2);
185 FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
187 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
188 spin_unlock_irq(&pd->lock);
197 spin_lock_irq(&pd->lock);
198 if (pd->curr_buf) {
199 vb2_buffer_done(&pd->curr_buf->vb2_buf, VB2_BUF_STATE_ERROR);
200 pd->curr_buf = NULL;
203 while (!list_empty(&pd->dmaq)) {
204 vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry);
208 spin_unlock_irq(&pd->lock);
214 struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
216 /* pd->vidq.streaming = 1 when dt3155_buf_queue() is invoked */
217 spin_lock_irq(&pd->lock);
218 if (pd->curr_buf)
219 list_add_tail(&vb->done_entry, &pd->dmaq);
221 pd->curr_buf = vbuf;
222 spin_unlock_irq(&pd->lock);
311 struct dt3155_priv *pd = video_drvdata(filp);
313 f->fmt.pix.width = pd->width;
314 f->fmt.pix.height = pd->height;
325 struct dt3155_priv *pd = video_drvdata(filp);
327 *norm = pd->std;
333 struct dt3155_priv *pd = video_drvdata(filp);
335 if (pd->std == norm)
337 if (vb2_is_busy(&pd->vidq))
339 pd->std = norm;
340 if (pd->std & V4L2_STD_525_60) {
341 pd->csr2 = VT_60HZ;
342 pd->width = 640;
343 pd->height = 480;
345 pd->csr2 = VT_50HZ;
346 pd->width = 768;
347 pd->height = 576;
370 struct dt3155_priv *pd = video_drvdata(filp);
372 *i = pd->input;
378 struct dt3155_priv *pd = video_drvdata(filp);
382 pd->input = i;
383 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
384 write_i2c_reg(pd->regs, AD_CMD, (i << 6) | (i << 4) | SYNC_LVL_3);
409 static int dt3155_init_board(struct dt3155_priv *pd)
411 struct pci_dev *pdev = pd->pdev;
419 FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
423 iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
424 iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT);
425 iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT);
426 iowrite32(0x00000020, pd->regs + FIFO_TRIGGER);
427 iowrite32(0x00000103, pd->regs + XFER_MODE);
428 iowrite32(0, pd->regs + RETRY_WAIT_CNT);
429 iowrite32(0, pd->regs + INT_CSR);
430 iowrite32(1, pd->regs + EVEN_FLD_MASK);
431 iowrite32(1, pd->regs + ODD_FLD_MASK);
432 iowrite32(0, pd->regs + MASK_LENGTH);
433 iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT);
434 iowrite32(0x01010101, pd->regs + IIC_CLK_DUR);
437 read_i2c_reg(pd->regs, DT_ID, &tmp);
442 write_i2c_reg(pd->regs, AD_ADDR, 0);
444 write_i2c_reg(pd->regs, AD_LUT, i);
448 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
449 write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
450 write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF);
451 write_i2c_reg(pd->regs, AD_CMD, 34);
452 write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF);
453 write_i2c_reg(pd->regs, AD_CMD, 0);
456 write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM);
458 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
459 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
461 write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL);
463 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
464 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
466 write_i2c_reg(pd->regs, CONFIG, pd->config); /* ACQ_MODE_EVEN */
469 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
470 write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
474 pd->regs + INT_CSR);
493 struct dt3155_priv *pd;
498 pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
499 if (!pd)
502 err = v4l2_device_register(&pdev->dev, &pd->v4l2_dev);
505 pd->vdev = dt3155_vdev;
506 pd->vdev.v4l2_dev = &pd->v4l2_dev;
507 video_set_drvdata(&pd->vdev, pd); /* for use in video_fops */
508 pd->pdev = pdev;
509 pd->std = V4L2_STD_625_50;
510 pd->csr2 = VT_50HZ;
511 pd->width = 768;
512 pd->height = 576;
513 INIT_LIST_HEAD(&pd->dmaq);
514 mutex_init(&pd->mux);
515 pd->vdev.lock = &pd->mux; /* for locking v4l2_file_operations */
516 pd->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
517 pd->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
518 pd->vidq.io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
519 pd->vidq.ops = &q_ops;
520 pd->vidq.mem_ops = &vb2_dma_contig_memops;
521 pd->vidq.drv_priv = pd;
522 pd->vidq.min_buffers_needed = 2;
523 pd->vidq.gfp_flags = GFP_DMA32;
524 pd->vidq.lock = &pd->mux; /* for locking v4l2_file_operations */
525 pd->vidq.dev = &pdev->dev;
526 pd->vdev.queue = &pd->vidq;
527 err = vb2_queue_init(&pd->vidq);
530 spin_lock_init(&pd->lock);
531 pd->config = ACQ_MODE_EVEN;
538 pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0));
539 if (!pd->regs) {
543 err = dt3155_init_board(pd);
546 err = request_irq(pd->pdev->irq, dt3155_irq_handler_even,
547 IRQF_SHARED, DT3155_NAME, pd);
550 err = video_register_device(&pd->vdev, VFL_TYPE_VIDEO, -1);
553 dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev.minor);
557 free_irq(pd->pdev->irq, pd);
559 pci_iounmap(pdev, pd->regs);
565 v4l2_device_unregister(&pd->v4l2_dev);
572 struct dt3155_priv *pd = container_of(v4l2_dev, struct dt3155_priv,
575 vb2_video_unregister_device(&pd->vdev);
576 free_irq(pd->pdev->irq, pd);
577 v4l2_device_unregister(&pd->v4l2_dev);
578 pci_iounmap(pdev, pd->regs);