Lines Matching refs:cx
13 void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)
21 cx18_writeb(cx, (u8) val, dst);
26 cx18_writew(cx, val2, dst);
31 cx18_writel(cx, val4, dst);
36 cx18_writew(cx, val2, dst);
41 cx18_writeb(cx, (u8) val, dst);
44 void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
46 cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
47 cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val;
48 cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
51 void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
53 cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val;
54 cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
57 void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
59 cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val);
60 cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | val;
61 cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
64 void cx18_sw2_irq_disable(struct cx18 *cx, u32 val)
66 cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) & ~val;
67 cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
70 void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val)
73 r = cx18_read_reg(cx, SW2_INT_ENABLE_CPU);
74 cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU);
77 void cx18_setup_page(struct cx18 *cx, u32 addr)
80 val = cx18_read_reg(cx, 0xD000F8);
82 cx18_write_reg(cx, val, 0xD000F8);