Lines Matching defs:link
212 cobalt_info("PCIe link capability 0x%08x: %s per lane and %u lanes\n",
215 cobalt_info("PCIe link control 0x%04x\n", ctrl);
216 cobalt_info("PCIe link status 0x%04x: %s per lane and %u lanes\n",
222 cobalt_info("PCIe bus link capability 0x%08x: %s per lane and %u lanes\n",
238 u16 link;
242 pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &link);
243 return FIELD_GET(PCI_EXP_LNKSTA_NLW, link);
249 u32 link;
253 pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &link);
254 return FIELD_GET(PCI_EXP_LNKCAP_MLW, link);
324 cobalt_warn("PCI Express link width is %d lanes.\n",