Lines Matching defs:state
4086 * TDA9887 series. Instead it has two tri-state input pins, S0 and S1,
4300 int state;
4312 state = (btread(BT848_GPIO_DATA) >> 21) & 7;
4315 switch (state) {
4320 pr_debug("PCI-8604PW in state %i, toggling pin\n",
4321 state);
4331 /* FIXME: If we are in state 7 and toggle GPIO[19] one
4332 more time, the CPLD goes into state 0, where PCI bus
4334 get out of that state. */
4339 pr_err("PCI-8604PW in unknown state %i\n", state);
4343 state = (state << 4) | ((btread(BT848_GPIO_DATA) >> 21) & 7);
4345 switch (state) {
4350 /* The transition from state 7 to state 0 is, as explained
4352 as we exit as soon as we are in state 7.
4357 state >> 4, state & 7);
4360 state &= 7;