Lines Matching refs:sd
41 struct v4l2_subdev sd;
56 static inline struct ths8200_state *to_state(struct v4l2_subdev *sd)
58 return container_of(sd, struct ths8200_state, sd);
71 static int ths8200_read(struct v4l2_subdev *sd, u8 reg)
73 struct i2c_client *client = v4l2_get_subdevdata(sd);
78 static int ths8200_write(struct v4l2_subdev *sd, u8 reg, u8 val)
80 struct i2c_client *client = v4l2_get_subdevdata(sd);
89 v4l2_err(sd, "I2C Write Problem\n");
97 ths8200_write_and_or(struct v4l2_subdev *sd, u8 reg,
100 ths8200_write(sd, reg, (ths8200_read(sd, reg) & clr_mask) | val_mask);
105 static int ths8200_g_register(struct v4l2_subdev *sd,
108 reg->val = ths8200_read(sd, reg->reg & 0xff);
114 static int ths8200_s_register(struct v4l2_subdev *sd,
117 ths8200_write(sd, reg->reg & 0xff, reg->val & 0xff);
123 static int ths8200_log_status(struct v4l2_subdev *sd)
125 struct ths8200_state *state = to_state(sd);
126 uint8_t reg_03 = ths8200_read(sd, THS8200_CHIP_CTL);
128 v4l2_info(sd, "----- Chip status -----\n");
129 v4l2_info(sd, "version: %u\n", state->chip_version);
130 v4l2_info(sd, "power: %s\n", (reg_03 & 0x0c) ? "off" : "on");
131 v4l2_info(sd, "reset: %s\n", (reg_03 & 0x01) ? "off" : "on");
132 v4l2_info(sd, "test pattern: %s\n",
134 v4l2_info(sd, "format: %ux%u\n",
135 ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_MSB) * 256 +
136 ths8200_read(sd, THS8200_DTG2_PIXEL_CNT_LSB),
137 (ths8200_read(sd, THS8200_DTG2_LINE_CNT_MSB) & 0x07) * 256 +
138 ths8200_read(sd, THS8200_DTG2_LINE_CNT_LSB));
139 v4l2_print_dv_timings(sd->name, "Configured format:",
145 static int ths8200_s_power(struct v4l2_subdev *sd, int on)
147 struct ths8200_state *state = to_state(sd);
149 v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
154 ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xf2, (on ? 0x00 : 0x0c));
172 static int ths8200_s_stream(struct v4l2_subdev *sd, int enable)
174 struct ths8200_state *state = to_state(sd);
177 ths8200_s_power(sd, true);
179 ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0xfe,
182 v4l2_dbg(1, debug, sd, "%s: %sable\n",
188 static void ths8200_core_init(struct v4l2_subdev *sd)
191 ths8200_write_and_or(sd, THS8200_CHIP_CTL, 0x3f, 0xc0);
198 ths8200_write(sd, THS8200_DATA_CNTL, 0x70);
203 ths8200_write(sd, THS8200_DTG1_MODE, 0x87);
210 ths8200_write(sd, THS8200_DTG1_Y_SYNC_MSB, 0x00);
211 ths8200_write(sd, THS8200_DTG1_CBCR_SYNC_MSB, 0x00);
214 static void ths8200_setup(struct v4l2_subdev *sd, struct v4l2_bt_timings *bt)
222 ths8200_s_stream(sd, false);
225 ths8200_write(sd, THS8200_DTG1_SPEC_A, bt->hsync);
226 ths8200_write(sd, THS8200_DTG1_SPEC_B, bt->hfrontporch);
230 ths8200_write(sd, THS8200_DTG1_SPEC_C, 0x00);
235 ths8200_write(sd, THS8200_DTG1_SPEC_D_LSB,
238 ths8200_write(sd, THS8200_DTG1_SPEC_E_LSB, 0x00);
243 ths8200_write(sd, THS8200_DTG1_SPEC_DEH_MSB,
247 ths8200_write(sd, THS8200_DTG1_SPEC_K_LSB, (bt->hfrontporch) & 0xff);
248 ths8200_write(sd, THS8200_DTG1_SPEC_K_MSB,
252 ths8200_write(sd, THS8200_DTG1_SPEC_G_LSB, (htotal(bt)/2) & 0xff);
253 ths8200_write(sd, THS8200_DTG1_SPEC_G_MSB,
257 ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_MSB, htotal(bt) >> 8);
258 ths8200_write(sd, THS8200_DTG1_TOT_PIXELS_LSB, htotal(bt) & 0xff);
264 ths8200_write(sd, THS8200_DTG1_FRAME_FIELD_SZ_MSB,
266 ths8200_write(sd, THS8200_DTG1_FRAME_SZ_LSB, vtotal(bt) & 0xff);
272 ths8200_write(sd, THS8200_DTG1_FIELD_SZ_LSB, 0xff);
289 ths8200_write_and_or(sd, THS8200_DTG2_BP1_2_MSB, 0x88,
292 ths8200_write(sd, THS8200_DTG2_BP3_4_MSB, ((vtotal(bt)) >> 4) & 0x70);
293 ths8200_write(sd, THS8200_DTG2_BP1_LSB, line_start_active_video & 0xff);
294 ths8200_write(sd, THS8200_DTG2_BP2_LSB, line_start_front_porch & 0xff);
295 ths8200_write(sd, THS8200_DTG2_BP3_LSB, (vtotal(bt)) & 0xff);
298 ths8200_write(sd, THS8200_DTG2_LINETYPE1, 0x90);
299 ths8200_write(sd, THS8200_DTG2_LINETYPE2, 0x90);
302 ths8200_write(sd, THS8200_DTG2_HLENGTH_LSB, bt->hsync & 0xff);
303 ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0x3f,
307 ths8200_write_and_or(sd, THS8200_DTG2_HLENGTH_LSB_HDLY_MSB, 0xe0,
309 ths8200_write(sd, THS8200_DTG2_HLENGTH_HDLY_LSB, htotal(bt));
312 ths8200_write(sd, THS8200_DTG2_VLENGTH1_LSB, (bt->vsync + 1) & 0xff);
313 ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0x3f,
317 ths8200_write_and_or(sd, THS8200_DTG2_VLENGTH1_MSB_VDLY1_MSB, 0xf8,
319 ths8200_write(sd, THS8200_DTG2_VDLY1_LSB, vtotal(bt) + 1);
324 ths8200_write(sd, THS8200_DTG2_VLENGTH2_LSB, 0x00);
325 ths8200_write(sd, THS8200_DTG2_VLENGTH2_MSB_VDLY2_MSB, 0x07);
326 ths8200_write(sd, THS8200_DTG2_VDLY2_LSB, 0xff);
330 ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_MSB, 0);
331 ths8200_write(sd, THS8200_DTG2_HS_IN_DLY_LSB, 0);
332 ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_MSB, 0);
333 ths8200_write(sd, THS8200_DTG2_VS_IN_DLY_LSB, 0);
349 ths8200_write(sd, THS8200_DTG2_CNTL, 0x44 | polarity);
352 ths8200_s_stream(sd, true);
354 v4l2_dbg(1, debug, sd, "%s: frame %dx%d, polarity %d\n"
361 static int ths8200_s_dv_timings(struct v4l2_subdev *sd,
364 struct ths8200_state *state = to_state(sd);
366 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
374 v4l2_dbg(1, debug, sd, "Unsupported format\n");
383 ths8200_setup(sd, &timings->bt);
388 static int ths8200_g_dv_timings(struct v4l2_subdev *sd,
391 struct ths8200_state *state = to_state(sd);
393 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
400 static int ths8200_enum_dv_timings(struct v4l2_subdev *sd,
410 static int ths8200_dv_timings_cap(struct v4l2_subdev *sd,
442 struct v4l2_subdev *sd;
453 sd = &state->sd;
454 v4l2_i2c_subdev_init(sd, client, &ths8200_ops);
456 state->chip_version = ths8200_read(sd, THS8200_VERSION);
457 v4l2_dbg(1, debug, sd, "chip version 0x%x\n", state->chip_version);
459 ths8200_core_init(sd);
461 error = v4l2_async_register_subdev(&state->sd);
465 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
473 struct v4l2_subdev *sd = i2c_get_clientdata(client);
474 struct ths8200_state *decoder = to_state(sd);
476 v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
479 ths8200_s_power(sd, false);
480 v4l2_async_unregister_subdev(&decoder->sd);