Lines Matching refs:val
41 #define PDATAF(val) FIELD_PREP(PDATAF_MASK, (val))
47 #define PDFMT(val) FIELD_PREP(GENMASK(7, 4), (val))
52 #define MCLK_HIGH(val) FIELD_PREP(MCLK_HIGH_MASK, (val))
53 #define MCLK_LOW(val) FIELD_PREP(MCLK_LOW_MASK, (val))
57 #define PLL_PRD(val) FIELD_PREP(PLL_PRD_MASK, (val))
59 #define PLL_FBD(val) FIELD_PREP(PLL_FBD_MASK, (val))
63 #define PLL_FRS(val) FIELD_PREP(PLL_FRS_MASK, (val))
70 #define MCLKDIV(val) FIELD_PREP(MCLKDIV_MASK, (val))
92 #define TCLK_ZEROCNT(val) FIELD_PREP(GENMASK(15, 8), (val))
93 #define TCLK_PREPARECNT(val) FIELD_PREP(GENMASK(6, 0), (val))
97 #define THS_ZEROCNT(val) FIELD_PREP(GENMASK(14, 8), (val))
98 #define THS_PREPARECNT(val) FIELD_PREP(GENMASK(6, 0), (val))
108 #define NOL(val) FIELD_PREP(GENMASK(2, 1), (val))
111 #define MODE(val) FIELD_PREP(GENMASK(31, 29), (val))
113 #define ADDRESS(val) FIELD_PREP(GENMASK(28, 24), (val))
115 #define DATA(val) FIELD_PREP(GENMASK(15, 0), (val))
311 static int tc358746_write(struct tc358746 *tc358746, u32 reg, u32 val)
319 err = regmap_bulk_write(tc358746->regmap, reg, &val, count);
327 static int tc358746_read(struct tc358746 *tc358746, u32 reg, u32 *val)
334 *val = 0;
336 err = regmap_bulk_read(tc358746->regmap, reg, val, count);
345 tc358746_update_bits(struct tc358746 *tc358746, u32 reg, u32 mask, u32 val)
355 tmp |= val & mask;
389 u32 val, mask;
392 err = tc358746_read(tc358746, PLLCTL1_REG, &val);
397 if (FIELD_GET(PLL_EN, val) == 1)
401 val = PLL_PRD(pre - 1) | PLL_FBD(mul - 1);
403 err = tc358746_update_bits(tc358746, PLLCTL0_REG, mask, val);
407 val = PLL_FRS(ilog2(post)) | RESETB | PLL_EN;
409 err = tc358746_update_bits(tc358746, PLLCTL1_REG, mask, val);
425 u32 val;
434 val = PDFMT(fmt->pdformat);
435 dev_dbg(dev, "DATAFMT: 0x%x\n", val);
436 err = tc358746_write(tc358746, DATAFMT_REG, val);
440 val = PDATAF(fmt->pdataf);
442 err = tc358746_update_bits(tc358746, CONFCTL_REG, PDATAF_MASK, val);
446 val = tc358746->vb_size / 32;
447 dev_dbg(dev, "FIFOCTL: %u (0x%x)\n", val, val);
448 err = tc358746_write(tc358746, FIFOCTL_REG, val);
453 val = mbusfmt->width * fmt->bpp / 8;
454 dev_dbg(dev, "WORDCNT: %u (0x%x)\n", val, val);
455 err = tc358746_write(tc358746, WORDCNT_REG, val);
490 u32 val, val2, lptxcnt;
498 val = tc358746_us_to_cnt(cfg->init, hf_clk) - 1;
499 dev_dbg(dev, "LINEINITCNT: %u (0x%x)\n", val, val);
500 err = tc358746_write(tc358746, LINEINITCNT_REG, val);
504 val = tc358746_ps_to_cnt(cfg->lpx, hs_byte_clk) - 1;
505 lptxcnt = val;
506 dev_dbg(dev, "LPTXTIMECNT: %u (0x%x)\n", val, val);
507 err = tc358746_write(tc358746, LPTXTIMECNT_REG, val);
511 val = tc358746_ps_to_cnt(cfg->clk_prepare, hs_byte_clk) - 1;
513 dev_dbg(dev, "TCLK_PREPARECNT: %u (0x%x)\n", val, val);
516 (u32)(TCLK_PREPARECNT(val) | TCLK_ZEROCNT(val2)));
518 TCLK_PREPARECNT(val) | TCLK_ZEROCNT(val2));
522 val = tc358746_ps_to_cnt(cfg->clk_trail, hs_byte_clk);
523 dev_dbg(dev, "TCLK_TRAILCNT: %u (0x%x)\n", val, val);
524 err = tc358746_write(tc358746, TCLK_TRAILCNT_REG, val);
528 val = tc358746_ps_to_cnt(cfg->hs_prepare, hs_byte_clk) - 1;
530 dev_dbg(dev, "THS_PREPARECNT: %u (0x%x)\n", val, val);
533 (u32)(THS_PREPARECNT(val) | THS_ZEROCNT(val2)));
535 THS_PREPARECNT(val) | THS_ZEROCNT(val2));
540 val = tc358746_us_to_cnt(cfg->wakeup, hs_byte_clk);
541 val = val / (lptxcnt + 1) - 1;
542 dev_dbg(dev, "TWAKEUP: %u (0x%x)\n", val, val);
543 err = tc358746_write(tc358746, TWAKEUP_REG, val);
547 val = tc358746_ps_to_cnt(cfg->clk_post, hs_byte_clk);
548 dev_dbg(dev, "TCLK_POSTCNT: %u (0x%x)\n", val, val);
549 err = tc358746_write(tc358746, TCLK_POSTCNT_REG, val);
553 val = tc358746_ps_to_cnt(cfg->hs_trail, hs_byte_clk);
554 dev_dbg(dev, "THS_TRAILCNT: %u (0x%x)\n", val, val);
555 err = tc358746_write(tc358746, THS_TRAILCNT_REG, val);
570 u32 reg, val;
579 val = enable ? 0 : LANEDISABLE;
580 dev_dbg(tc358746->sd.dev, "CLW_CNTRL: 0x%x\n", val);
581 err = tc358746_write(tc358746, CLW_CNTRL_REG, val);
588 val = (enable && lane < lanes) ? 0 : LANEDISABLE;
590 dev_dbg(tc358746->sd.dev, "D%uW_CNTRL: 0x%x\n", lane, val);
591 err = tc358746_write(tc358746, reg, val);
596 val = 0;
599 val |= BIT(0);
603 val |= BIT(lane);
606 dev_dbg(tc358746->sd.dev, "HSTXVREGEN: 0x%x\n", val);
608 return tc358746_write(tc358746, HSTXVREGEN_REG, val);
991 u32 val;
1000 err = tc358746_read(tc358746, reg->reg, &val);
1001 reg->val = val;
1017 tc358746_write(tc358746, (u32)reg->reg, (u32)reg->val);
1060 u32 val;
1064 val = MCLK_HIGH(div - 1) | MCLK_LOW(div - 1);
1065 dev_dbg(tc358746->sd.dev, "MCLKCTL: %u (0x%x)\n", val, val);
1066 err = tc358746_write(tc358746, MCLKCTL_REG, val);
1071 val = MCLKDIV(MCLKDIV_8);
1073 val = MCLKDIV(MCLKDIV_4);
1075 val = MCLKDIV(MCLKDIV_2);
1077 dev_dbg(tc358746->sd.dev, "CLKCTL[MCLKDIV]: %u (0x%x)\n", val, val);
1079 return tc358746_update_bits(tc358746, CLKCTL_REG, MCLKDIV_MASK, val);
1185 u32 val;
1188 err = tc358746_read(tc358746, MCLKCTL_REG, &val);
1192 postdiv = FIELD_GET(MCLK_LOW_MASK, val) + 1;
1193 postdiv += FIELD_GET(MCLK_HIGH_MASK, val) + 1;
1195 err = tc358746_read(tc358746, CLKCTL_REG, &val);
1199 prediv = FIELD_GET(MCLKDIV_MASK, val);
1362 u32 val;
1379 err = tc358746_read(tc358746, CHIPID_REG, &val);
1385 chipid = FIELD_GET(CHIPID, val);