Lines Matching defs:tc358746
141 struct tc358746 {
171 static inline struct tc358746 *to_tc358746(struct v4l2_subdev *sd)
173 return container_of(sd, struct tc358746, sd);
176 static inline struct tc358746 *clk_hw_to_tc358746(struct clk_hw *hw)
178 return container_of(hw, struct tc358746, mclk_hw);
301 .name = "tc358746",
311 static int tc358746_write(struct tc358746 *tc358746, u32 reg, u32 val)
319 err = regmap_bulk_write(tc358746->regmap, reg, &val, count);
321 dev_err(tc358746->sd.dev,
327 static int tc358746_read(struct tc358746 *tc358746, u32 reg, u32 *val)
336 err = regmap_bulk_read(tc358746->regmap, reg, val, count);
338 dev_err(tc358746->sd.dev,
345 tc358746_update_bits(struct tc358746 *tc358746, u32 reg, u32 mask, u32 val)
350 err = tc358746_read(tc358746, reg, &orig);
357 return tc358746_write(tc358746, reg, tmp);
360 static int tc358746_set_bits(struct tc358746 *tc358746, u32 reg, u32 bits)
362 return tc358746_update_bits(tc358746, reg, bits, bits);
365 static int tc358746_clear_bits(struct tc358746 *tc358746, u32 reg, u32 bits)
367 return tc358746_update_bits(tc358746, reg, bits, 0);
370 static int tc358746_sw_reset(struct tc358746 *tc358746)
374 err = tc358746_set_bits(tc358746, SYSCTL_REG, SRESET);
380 return tc358746_clear_bits(tc358746, SYSCTL_REG, SRESET);
384 tc358746_apply_pll_config(struct tc358746 *tc358746)
386 u8 post = tc358746->pll_post_div;
387 u16 pre = tc358746->pll_pre_div;
388 u16 mul = tc358746->pll_mul;
392 err = tc358746_read(tc358746, PLLCTL1_REG, &val);
403 err = tc358746_update_bits(tc358746, PLLCTL0_REG, mask, val);
409 err = tc358746_update_bits(tc358746, PLLCTL1_REG, mask, val);
415 return tc358746_set_bits(tc358746, PLLCTL1_REG, CKEN);
418 static int tc358746_apply_misc_config(struct tc358746 *tc358746)
421 struct v4l2_subdev *sd = &tc358746->sd;
436 err = tc358746_write(tc358746, DATAFMT_REG, val);
442 err = tc358746_update_bits(tc358746, CONFCTL_REG, PDATAF_MASK, val);
446 val = tc358746->vb_size / 32;
448 err = tc358746_write(tc358746, FIFOCTL_REG, val);
455 err = tc358746_write(tc358746, WORDCNT_REG, val);
483 static int tc358746_apply_dphy_config(struct tc358746 *tc358746)
485 struct phy_configure_opts_mipi_dphy *cfg = &tc358746->dphy_cfg;
486 bool non_cont_clk = !!(tc358746->csi_vep.bus.mipi_csi2.flags &
488 struct device *dev = tc358746->sd.dev;
500 err = tc358746_write(tc358746, LINEINITCNT_REG, val);
507 err = tc358746_write(tc358746, LPTXTIMECNT_REG, val);
517 err = tc358746_write(tc358746, TCLK_HEADERCNT_REG,
524 err = tc358746_write(tc358746, TCLK_TRAILCNT_REG, val);
534 err = tc358746_write(tc358746, THS_HEADERCNT_REG,
543 err = tc358746_write(tc358746, TWAKEUP_REG, val);
549 err = tc358746_write(tc358746, TCLK_POSTCNT_REG, val);
555 err = tc358746_write(tc358746, THS_TRAILCNT_REG, val);
561 return tc358746_write(tc358746, TXOPTIONCNTRL_REG, non_cont_clk ? 0 : 1);
566 static int tc358746_enable_csi_lanes(struct tc358746 *tc358746, int enable)
568 unsigned int lanes = tc358746->dphy_cfg.lanes;
573 err = tc358746_update_bits(tc358746, CONFCTL_REG, DATALANE_MASK,
580 dev_dbg(tc358746->sd.dev, "CLW_CNTRL: 0x%x\n", val);
581 err = tc358746_write(tc358746, CLW_CNTRL_REG, val);
590 dev_dbg(tc358746->sd.dev, "D%uW_CNTRL: 0x%x\n", lane, val);
591 err = tc358746_write(tc358746, reg, val);
606 dev_dbg(tc358746->sd.dev, "HSTXVREGEN: 0x%x\n", val);
608 return tc358746_write(tc358746, HSTXVREGEN_REG, val);
611 static int tc358746_enable_csi_module(struct tc358746 *tc358746, int enable)
613 unsigned int lanes = tc358746->dphy_cfg.lanes;
622 return tc358746_sw_reset(tc358746);
624 err = tc358746_write(tc358746, STARTCNTRL_REG, START);
628 err = tc358746_write(tc358746, CSI_START_REG, STRT);
633 return tc358746_write(tc358746, CSI_CONFW_REG,
639 static int tc358746_enable_parallel_port(struct tc358746 *tc358746, int enable)
644 err = tc358746_write(tc358746, PP_MISC_REG, 0);
648 return tc358746_set_bits(tc358746, CONFCTL_REG, PPEN);
651 err = tc358746_set_bits(tc358746, PP_MISC_REG, FRMSTOP);
655 err = tc358746_clear_bits(tc358746, CONFCTL_REG, PPEN);
659 return tc358746_set_bits(tc358746, PP_MISC_REG, RSTPTR);
673 struct tc358746 *tc358746 = to_tc358746(sd);
679 src = tc358746_get_remote_sd(&tc358746->pads[TC358746_SINK]);
688 err = tc358746_apply_dphy_config(tc358746);
692 err = tc358746_apply_misc_config(tc358746);
696 err = tc358746_enable_csi_lanes(tc358746, 1);
700 err = tc358746_enable_csi_module(tc358746, 1);
704 err = tc358746_enable_parallel_port(tc358746, 1);
725 err = tc358746_enable_csi_lanes(tc358746, 0);
729 err = tc358746_enable_csi_module(tc358746, 0);
733 err = tc358746_enable_parallel_port(tc358746, 0);
806 static unsigned long tc358746_find_pll_settings(struct tc358746 *tc358746,
811 struct device *dev = tc358746->sd.dev;
868 tc358746->pll_post_div = postdiv;
869 tc358746->pll_pre_div = p_best;
870 tc358746->pll_mul = m_best;
889 struct tc358746 *tc358746 = to_tc358746(sd);
912 dev_err(tc358746->sd.dev,
920 csi_bitrate = tc358746->dphy_cfg.lanes * tc358746->pll_rate;
922 dev_dbg(tc358746->sd.dev,
935 tc358746->vb_size = TC358746_VB_DEFAULT_SIZE;
961 tc358746->vb_size = round_up(fifo_sz, 32);
964 dev_dbg(tc358746->sd.dev,
966 fifo_sz, tc358746->vb_size);
970 return tc358746->vb_size > TC358746_VB_MAX_SIZE ? -EINVAL : 0;
976 struct tc358746 *tc358746 = to_tc358746(sd);
982 config->bus.mipi_csi2 = tc358746->csi_vep.bus.mipi_csi2;
990 struct tc358746 *tc358746 = to_tc358746(sd);
1000 err = tc358746_read(tc358746, reg->reg, &val);
1012 struct tc358746 *tc358746 = to_tc358746(sd);
1017 tc358746_write(tc358746, (u32)reg->reg, (u32)reg->val);
1058 struct tc358746 *tc358746 = clk_hw_to_tc358746(hw);
1063 div = tc358746->mclk_postdiv / 2;
1065 dev_dbg(tc358746->sd.dev, "MCLKCTL: %u (0x%x)\n", val, val);
1066 err = tc358746_write(tc358746, MCLKCTL_REG, val);
1070 if (tc358746->mclk_prediv == 8)
1072 else if (tc358746->mclk_prediv == 4)
1077 dev_dbg(tc358746->sd.dev, "CLKCTL[MCLKDIV]: %u (0x%x)\n", val, val);
1079 return tc358746_update_bits(tc358746, CLKCTL_REG, MCLKDIV_MASK, val);
1084 struct tc358746 *tc358746 = clk_hw_to_tc358746(hw);
1086 tc358746_write(tc358746, MCLKCTL_REG, 0);
1090 tc358746_find_mclk_settings(struct tc358746 *tc358746, unsigned long mclk_rate)
1092 unsigned long pll_rate = tc358746->pll_rate;
1095 struct device *dev = tc358746->sd.dev;
1120 if (mclk_rate == tc358746->mclk_rate)
1166 tc358746->mclk_prediv = mclk_prediv;
1167 tc358746->mclk_postdiv = mclk_postdiv;
1168 tc358746->mclk_rate = best_mclk_rate;
1183 struct tc358746 *tc358746 = clk_hw_to_tc358746(hw);
1188 err = tc358746_read(tc358746, MCLKCTL_REG, &val);
1195 err = tc358746_read(tc358746, CLKCTL_REG, &val);
1207 return tc358746->pll_rate / (prediv * postdiv);
1213 struct tc358746 *tc358746 = clk_hw_to_tc358746(hw);
1215 *parent_rate = tc358746->pll_rate;
1217 return tc358746_find_mclk_settings(tc358746, rate);
1223 struct tc358746 *tc358746 = clk_hw_to_tc358746(hw);
1225 tc358746_find_mclk_settings(tc358746, rate);
1238 static int tc358746_setup_mclk_provider(struct tc358746 *tc358746)
1241 struct device *dev = tc358746->sd.dev;
1250 tc358746->mclk_postdiv = 512;
1251 tc358746->mclk_prediv = 8;
1253 mclk_name = "tc358746-mclk";
1258 tc358746->mclk_hw.init = &mclk_initdata;
1260 err = devm_clk_hw_register(dev, &tc358746->mclk_hw);
1267 &tc358746->mclk_hw);
1275 tc358746_init_subdev(struct tc358746 *tc358746, struct i2c_client *client)
1277 struct v4l2_subdev *sd = &tc358746->sd;
1285 tc358746->pads[TC358746_SINK].flags = MEDIA_PAD_FL_SINK;
1286 tc358746->pads[TC358746_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1288 tc358746->pads);
1300 tc358746_init_output_port(struct tc358746 *tc358746, unsigned long refclk)
1302 struct device *dev = tc358746->sd.dev;
1317 vep = &tc358746->csi_vep;
1336 tc358746->pll_rate = tc358746_find_pll_settings(tc358746, refclk,
1338 if (!tc358746->pll_rate) {
1343 err = phy_mipi_dphy_get_default_config_for_hsclk(tc358746->pll_rate,
1344 csi_lanes, &tc358746->dphy_cfg);
1348 tc358746->vb_size = TC358746_VB_DEFAULT_SIZE;
1358 static int tc358746_init_hw(struct tc358746 *tc358746)
1360 struct device *dev = tc358746->sd.dev;
1372 err = tc358746_sw_reset(tc358746);
1379 err = tc358746_read(tc358746, CHIPID_REG, &val);
1394 static int tc358746_init_controls(struct tc358746 *tc358746)
1396 u64 *link_frequencies = tc358746->csi_vep.link_frequencies;
1400 err = v4l2_ctrl_handler_init(&tc358746->ctrl_hdl, 1);
1410 ctrl = v4l2_ctrl_new_int_menu(&tc358746->ctrl_hdl, NULL,
1416 err = tc358746->ctrl_hdl.error;
1418 v4l2_ctrl_handler_free(&tc358746->ctrl_hdl);
1422 tc358746->sd.ctrl_handler = &tc358746->ctrl_hdl;
1431 struct tc358746 *tc358746 =
1432 container_of(notifier, struct tc358746, notifier);
1434 struct media_pad *sink = &tc358746->pads[TC358746_SINK];
1443 static int tc358746_async_register(struct tc358746 *tc358746)
1452 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(tc358746->sd.dev),
1463 v4l2_async_subdev_nf_init(&tc358746->notifier, &tc358746->sd);
1464 asd = v4l2_async_nf_add_fwnode_remote(&tc358746->notifier, ep,
1473 tc358746->notifier.ops = &tc358746_notify_ops;
1475 err = v4l2_async_nf_register(&tc358746->notifier);
1479 err = v4l2_async_register_subdev(&tc358746->sd);
1486 v4l2_async_nf_unregister(&tc358746->notifier);
1488 v4l2_async_nf_cleanup(&tc358746->notifier);
1496 struct tc358746 *tc358746;
1501 tc358746 = devm_kzalloc(&client->dev, sizeof(*tc358746), GFP_KERNEL);
1502 if (!tc358746)
1505 tc358746->regmap = devm_regmap_init_i2c(client, &tc358746_regmap_config);
1506 if (IS_ERR(tc358746->regmap))
1507 return dev_err_probe(dev, PTR_ERR(tc358746->regmap),
1510 tc358746->refclk = devm_clk_get(dev, "refclk");
1511 if (IS_ERR(tc358746->refclk))
1512 return dev_err_probe(dev, PTR_ERR(tc358746->refclk),
1515 err = clk_prepare_enable(tc358746->refclk);
1520 refclk = clk_get_rate(tc358746->refclk);
1521 clk_disable_unprepare(tc358746->refclk);
1527 tc358746->supplies[i].supply = tc358746_supplies[i];
1530 tc358746->supplies);
1534 tc358746->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1536 if (IS_ERR(tc358746->reset_gpio))
1537 return dev_err_probe(dev, PTR_ERR(tc358746->reset_gpio),
1540 err = tc358746_init_subdev(tc358746, client);
1544 err = tc358746_init_output_port(tc358746, refclk);
1552 err = tc358746_init_controls(tc358746);
1556 dev_set_drvdata(dev, tc358746);
1563 err = tc358746_init_hw(tc358746);
1567 err = tc358746_setup_mclk_provider(tc358746);
1571 err = tc358746_async_register(tc358746);
1584 v4l2_ctrl_handler_free(&tc358746->ctrl_hdl);
1586 v4l2_fwnode_endpoint_free(&tc358746->csi_vep);
1588 v4l2_subdev_cleanup(&tc358746->sd);
1589 media_entity_cleanup(&tc358746->sd.entity);
1597 struct tc358746 *tc358746 = to_tc358746(sd);
1600 v4l2_ctrl_handler_free(&tc358746->ctrl_hdl);
1601 v4l2_fwnode_endpoint_free(&tc358746->csi_vep);
1602 v4l2_async_nf_unregister(&tc358746->notifier);
1603 v4l2_async_nf_cleanup(&tc358746->notifier);
1614 struct tc358746 *tc358746 = dev_get_drvdata(dev);
1617 clk_disable_unprepare(tc358746->refclk);
1620 tc358746->supplies);
1622 clk_prepare_enable(tc358746->refclk);
1629 struct tc358746 *tc358746 = dev_get_drvdata(dev);
1632 gpiod_set_value(tc358746->reset_gpio, 1);
1635 tc358746->supplies);
1642 gpiod_set_value(tc358746->reset_gpio, 0);
1644 err = clk_prepare_enable(tc358746->refclk);
1655 err = tc358746_apply_pll_config(tc358746);
1662 clk_disable_unprepare(tc358746->refclk);
1665 tc358746->supplies);
1673 { .compatible = "toshiba,tc358746" },
1680 .name = "tc358746",