Lines Matching refs:sd
73 struct v4l2_subdev sd;
102 static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
104 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
106 static inline struct tc358743_state *to_state(struct v4l2_subdev *sd)
108 return container_of(sd, struct tc358743_state, sd);
113 static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
115 struct tc358743_state *state = to_state(sd);
136 v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed: %d\n",
141 static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
143 struct tc358743_state *state = to_state(sd);
151 v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
168 v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed: %d\n",
178 v4l2_info(sd, "I2C write 0x%04x = 0x%02x",
182 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x",
186 v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x",
190 v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
195 static noinline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n)
199 i2c_rd(sd, reg, (u8 __force *)&val, n);
204 static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n)
208 i2c_wr(sd, reg, (u8 __force *)&raw, n);
211 static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
213 return i2c_rdreg(sd, reg, 1);
216 static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
218 i2c_wrreg(sd, reg, val, 1);
221 static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
224 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1);
227 static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
229 return i2c_rdreg(sd, reg, 2);
232 static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
234 i2c_wrreg(sd, reg, val, 2);
237 static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
239 i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 2) & mask) | val, 2);
242 static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
244 return i2c_rdreg(sd, reg, 4);
247 static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
249 i2c_wrreg(sd, reg, val, 4);
254 static inline bool is_hdmi(struct v4l2_subdev *sd)
256 return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
259 static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
261 return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
264 static inline bool no_signal(struct v4l2_subdev *sd)
266 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
269 static inline bool no_sync(struct v4l2_subdev *sd)
271 return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
274 static inline bool audio_present(struct v4l2_subdev *sd)
276 return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
279 static int get_audio_sampling_rate(struct v4l2_subdev *sd)
287 if (no_signal(sd))
290 return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
304 static int tc358743_get_detected_timings(struct v4l2_subdev *sd,
312 if (no_signal(sd)) {
313 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
316 if (no_sync(sd)) {
317 v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__);
322 bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ?
325 width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) +
326 i2c_rd8(sd, DE_WIDTH_H_LO);
327 height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) +
328 i2c_rd8(sd, DE_WIDTH_V_LO);
329 frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) +
330 i2c_rd8(sd, H_SIZE_LO);
331 frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) +
332 i2c_rd8(sd, V_SIZE_LO)) / 2;
335 frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
336 i2c_rd8(sd, FV_CNT_LO);
361 struct v4l2_subdev *sd = &state->sd;
363 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
365 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
368 static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
370 v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ?
374 i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, KEY_RD_CMD);
376 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 0);
378 i2c_wr8_and_or(sd, HDCP_REG1, 0xff,
382 i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
385 i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION,
390 static void tc358743_disable_edid(struct v4l2_subdev *sd)
392 struct tc358743_state *state = to_state(sd);
394 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
400 i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
403 static void tc358743_enable_edid(struct v4l2_subdev *sd)
405 struct tc358743_state *state = to_state(sd);
408 v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__);
409 tc358743_s_ctrl_detect_tx_5v(sd);
413 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
419 tc358743_enable_interrupts(sd, true);
420 tc358743_s_ctrl_detect_tx_5v(sd);
423 static void tc358743_erase_bksv(struct v4l2_subdev *sd)
428 i2c_wr8(sd, BKSV + i, 0);
433 static void print_avi_infoframe(struct v4l2_subdev *sd)
435 struct i2c_client *client = v4l2_get_subdevdata(sd);
440 if (!is_hdmi(sd)) {
441 v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n");
445 i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI));
448 v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__);
457 static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
459 struct tc358743_state *state = to_state(sd);
462 tx_5v_power_present(sd));
465 static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
467 struct tc358743_state *state = to_state(sd);
470 get_audio_sampling_rate(sd));
473 static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd)
475 struct tc358743_state *state = to_state(sd);
478 audio_present(sd));
481 static int tc358743_update_controls(struct v4l2_subdev *sd)
485 ret |= tc358743_s_ctrl_detect_tx_5v(sd);
486 ret |= tc358743_s_ctrl_audio_sampling_rate(sd);
487 ret |= tc358743_s_ctrl_audio_present(sd);
494 static void tc358743_reset_phy(struct v4l2_subdev *sd)
496 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
498 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
499 i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
502 static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask)
504 u16 sysctl = i2c_rd16(sd, SYSCTL);
506 i2c_wr16(sd, SYSCTL, sysctl | mask);
507 i2c_wr16(sd, SYSCTL, sysctl & ~mask);
510 static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable)
512 i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP,
516 static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
518 struct tc358743_state *state = to_state(sd);
520 v4l2_dbg(3, debug, sd, "%s: %sable\n",
527 i2c_wr32(sd, TXOPTIONCNTRL, 0);
529 i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
531 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE);
535 i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE);
539 i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN),
544 static void tc358743_set_pll(struct v4l2_subdev *sd)
546 struct tc358743_state *state = to_state(sd);
548 u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
549 u16 pllctl1 = i2c_rd16(sd, PLLCTL1);
554 v4l2_dbg(2, debug, sd, "%s:\n", __func__);
570 v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__);
571 tc358743_sleep_mode(sd, true);
572 i2c_wr16(sd, PLLCTL0, pllctl0_new);
573 i2c_wr16_and_or(sd, PLLCTL1,
578 i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN);
579 tc358743_sleep_mode(sd, false);
583 static void tc358743_set_ref_clk(struct v4l2_subdev *sd)
585 struct tc358743_state *state = to_state(sd);
598 i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff);
599 i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8);
601 i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND,
606 i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff);
607 i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8);
610 i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff);
611 i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8);
614 i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff);
615 i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8);
616 i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16);
618 i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD,
628 i2c_wr16(sd, CECHCLK, cec_freq);
629 i2c_wr16(sd, CECLCLK, cec_freq);
632 static void tc358743_set_csi_color_space(struct v4l2_subdev *sd)
634 struct tc358743_state *state = to_state(sd);
638 v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__);
639 i2c_wr8_and_or(sd, VOUT_SET2,
642 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
645 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT,
650 v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__);
651 i2c_wr8_and_or(sd, VOUT_SET2,
654 i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
657 i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0);
661 v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
666 static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd)
668 struct tc358743_state *state = to_state(sd);
679 static void tc358743_set_csi(struct v4l2_subdev *sd)
681 struct tc358743_state *state = to_state(sd);
683 unsigned lanes = tc358743_num_csi_lanes_needed(sd);
685 v4l2_dbg(3, debug, sd, "%s:\n", __func__);
689 tc358743_reset(sd, MASK_CTXRST);
692 i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
694 i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
696 i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
698 i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
700 i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);
702 i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
703 i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
704 i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
705 i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt);
706 i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
707 i2c_wr32(sd, TWAKEUP, pdata->twakeup);
708 i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt);
709 i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
710 i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);
712 i2c_wr32(sd, HSTXVREGEN,
719 i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags &
721 i2c_wr32(sd, STARTCNTRL, MASK_START);
722 i2c_wr32(sd, CSI_START, MASK_STRT);
724 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
732 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
736 i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR |
739 i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
743 static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd)
745 struct tc358743_state *state = to_state(sd);
750 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0);
751 i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) |
753 i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn,
760 i2c_wr8(sd, PHY_BIAS, 0x40);
761 i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a));
762 i2c_wr8(sd, AVM_CTL, 45);
763 i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V,
765 i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST),
770 i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);
773 static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd)
775 struct tc358743_state *state = to_state(sd);
778 i2c_wr8(sd, FORCE_MUTE, 0x00);
779 i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 |
782 i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9);
783 i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2);
784 i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500));
785 i2c_wr8(sd, FS_MUTE, 0x00);
786 i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE);
787 i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE);
788 i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM);
789 i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM);
790 i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S);
791 i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100));
794 i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 |
799 static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd)
802 i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE |
806 i2c_wr8(sd, NO_PKT_LIMIT, 0x2c);
807 i2c_wr8(sd, NO_PKT_CLR, 0x53);
808 i2c_wr8(sd, ERR_PK_LIMIT, 0x01);
809 i2c_wr8(sd, NO_PKT_LIMIT2, 0x30);
810 i2c_wr8(sd, NO_GDB_LIMIT, 0x10);
813 static void tc358743_initial_setup(struct v4l2_subdev *sd)
815 struct tc358743_state *state = to_state(sd);
822 i2c_wr16_and_or(sd, SYSCTL, ~(MASK_IRRST | MASK_CECRST),
825 tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST);
827 tc358743_reset(sd, MASK_CECRST);
829 tc358743_sleep_mode(sd, false);
831 i2c_wr16(sd, FIFOCTL, pdata->fifo_level);
833 tc358743_set_ref_clk(sd);
835 i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE,
837 i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC);
839 tc358743_set_hdmi_phy(sd);
840 tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp);
841 tc358743_set_hdmi_audio(sd);
842 tc358743_set_hdmi_info_frame_mode(sd);
845 i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0);
847 i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE,
849 i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT);
858 struct v4l2_subdev *sd = &state->sd;
860 i2c_wr32(sd, CECIMSK, enable ? MASK_CECTIM | MASK_CECRIM : 0);
861 i2c_wr32(sd, CECICLR, MASK_CECTICLR | MASK_CECRICLR);
862 i2c_wr32(sd, CECEN, enable);
864 i2c_wr32(sd, CECREN, MASK_CECREN);
872 struct v4l2_subdev *sd = &state->sd;
875 reg = i2c_rd32(sd, CECRCTL1);
880 i2c_wr32(sd, CECRCTL1, reg);
887 struct v4l2_subdev *sd = &state->sd;
891 la = i2c_rd32(sd, CECADD);
894 i2c_wr32(sd, CECADD, la);
902 struct v4l2_subdev *sd = &state->sd;
905 i2c_wr32(sd, CECTCTL,
909 i2c_wr32(sd, CECTBUF1 + i * 4,
911 i2c_wr32(sd, CECTEN, MASK_CECTEN);
922 static void tc358743_cec_handler(struct v4l2_subdev *sd, u16 intstatus,
925 struct tc358743_state *state = to_state(sd);
929 cec_rxint = i2c_rd32(sd, CECRSTAT);
930 cec_txint = i2c_rd32(sd, CECTSTAT);
936 i2c_wr32(sd, CECICLR, clr);
965 v = i2c_rd32(sd, CECRCTR);
970 v = i2c_rd32(sd, CECRBUF1 + i * 4);
977 i2c_wr16(sd, INTSTATUS,
985 static void tc358743_format_change(struct v4l2_subdev *sd)
987 struct tc358743_state *state = to_state(sd);
994 if (tc358743_get_detected_timings(sd, &timings)) {
995 enable_stream(sd, false);
997 v4l2_dbg(1, debug, sd, "%s: No signal\n",
1001 enable_stream(sd, false);
1004 v4l2_print_dv_timings(sd->name,
1009 if (sd->devnode)
1010 v4l2_subdev_notify_event(sd, &tc358743_ev_fmt);
1013 static void tc358743_init_interrupts(struct v4l2_subdev *sd)
1019 i2c_wr8(sd, i, 0xff);
1021 i2c_wr16(sd, INTSTATUS, 0xffff);
1024 static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
1027 v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__,
1031 i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET |
1033 i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG);
1034 i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK |
1036 i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END);
1037 i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG);
1039 i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff);
1040 i2c_wr8(sd, CLK_INTM, 0xff);
1041 i2c_wr8(sd, CBIT_INTM, 0xff);
1042 i2c_wr8(sd, AUDIO_INTM, 0xff);
1043 i2c_wr8(sd, MISC_INTM, 0xff);
1047 static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd,
1050 u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM);
1051 u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask;
1053 i2c_wr8(sd, AUDIO_INT, audio_int);
1055 v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int);
1057 tc358743_s_ctrl_audio_sampling_rate(sd);
1058 tc358743_s_ctrl_audio_present(sd);
1061 static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled)
1063 v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR));
1065 i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER);
1068 static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd,
1071 u8 misc_int_mask = i2c_rd8(sd, MISC_INTM);
1072 u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask;
1074 i2c_wr8(sd, MISC_INT, misc_int);
1076 v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int);
1082 if (no_sync(sd) || no_signal(sd)) {
1083 tc358743_reset_phy(sd);
1084 tc358743_erase_bksv(sd);
1087 tc358743_format_change(sd);
1095 v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n",
1100 static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd,
1103 u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM);
1104 u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask;
1106 i2c_wr8(sd, CBIT_INT, cbit_int);
1108 v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int);
1112 v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n",
1114 tc358743_s_ctrl_audio_sampling_rate(sd);
1123 v4l2_dbg(1, debug, sd, "%s: Audio present changed\n",
1125 tc358743_s_ctrl_audio_present(sd);
1133 v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n",
1138 static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled)
1140 u8 clk_int_mask = i2c_rd8(sd, CLK_INTM);
1141 u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask;
1144 i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG);
1146 v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int);
1150 v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n",
1159 if (!no_signal(sd) && !no_sync(sd))
1160 tc358743_format_change(sd);
1168 v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n",
1173 static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled)
1175 struct tc358743_state *state = to_state(sd);
1176 u8 sys_int_mask = i2c_rd8(sd, SYS_INTM);
1177 u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask;
1179 i2c_wr8(sd, SYS_INT, sys_int);
1181 v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int);
1184 bool tx_5v = tx_5v_power_present(sd);
1186 v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n",
1190 tc358743_enable_edid(sd);
1192 tc358743_enable_interrupts(sd, false);
1193 tc358743_disable_edid(sd);
1195 tc358743_erase_bksv(sd);
1196 tc358743_update_controls(sd);
1205 v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n",
1211 if (no_sync(sd) || no_signal(sd)) {
1212 tc358743_reset_phy(sd);
1213 tc358743_erase_bksv(sd);
1222 v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n",
1226 i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON);
1234 v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n",
1241 static int tc358743_log_status(struct v4l2_subdev *sd)
1243 struct tc358743_state *state = to_state(sd);
1245 uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS);
1246 uint16_t sysctl = i2c_rd16(sd, SYSCTL);
1247 u8 vi_status3 = i2c_rd8(sd, VI_STATUS3);
1254 v4l2_info(sd, "-----Chip status-----\n");
1255 v4l2_info(sd, "Chip ID: 0x%02x\n",
1256 (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8);
1257 v4l2_info(sd, "Chip revision: 0x%02x\n",
1258 i2c_rd16(sd, CHIPID) & MASK_REVID);
1259 v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n",
1264 v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off");
1265 v4l2_info(sd, "Cable detected (+5V power): %s\n",
1267 v4l2_info(sd, "DDC lines enabled: %s\n",
1268 (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ?
1270 v4l2_info(sd, "Hotplug enabled: %s\n",
1271 (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?
1273 v4l2_info(sd, "CEC enabled: %s\n",
1274 (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no");
1275 v4l2_info(sd, "-----Signal status-----\n");
1276 v4l2_info(sd, "TMDS signal detected: %s\n",
1278 v4l2_info(sd, "Stable sync signal: %s\n",
1280 v4l2_info(sd, "PHY PLL locked: %s\n",
1282 v4l2_info(sd, "PHY DE detected: %s\n",
1285 if (tc358743_get_detected_timings(sd, &timings)) {
1286 v4l2_info(sd, "No video detected\n");
1288 v4l2_print_dv_timings(sd->name, "Detected format: ", &timings,
1291 v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings,
1294 v4l2_info(sd, "-----CSI-TX status-----\n");
1295 v4l2_info(sd, "Lanes needed: %d\n",
1296 tc358743_num_csi_lanes_needed(sd));
1297 v4l2_info(sd, "Lanes in use: %d\n",
1299 v4l2_info(sd, "Waiting for particular sync signal: %s\n",
1300 (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?
1302 v4l2_info(sd, "Transmit mode: %s\n",
1303 (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?
1305 v4l2_info(sd, "Receive mode: %s\n",
1306 (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?
1308 v4l2_info(sd, "Stopped: %s\n",
1309 (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?
1311 v4l2_info(sd, "Color space: %s\n",
1317 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
1318 v4l2_info(sd, "HDCP encrypted content: %s\n",
1320 v4l2_info(sd, "Input color space: %s %s range\n",
1323 if (!is_hdmi(sd))
1325 v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" :
1327 v4l2_info(sd, "Deep color mode: %d-bits per channel\n",
1328 deep_color_mode[(i2c_rd8(sd, VI_STATUS1) &
1330 print_avi_infoframe(sd);
1336 static void tc358743_print_register_map(struct v4l2_subdev *sd)
1338 v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n");
1339 v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n");
1340 v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n");
1341 v4l2_info(sd, "0x0400-0x05FF: Reserved\n");
1342 v4l2_info(sd, "0x0600-0x06FF: CEC Register\n");
1343 v4l2_info(sd, "0x0700-0x84FF: Reserved\n");
1344 v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n");
1345 v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n");
1346 v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n");
1347 v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n");
1348 v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n");
1349 v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n");
1350 v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n");
1351 v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n");
1352 v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n");
1353 v4l2_info(sd, "0x9300- : Reserved\n");
1369 static int tc358743_g_register(struct v4l2_subdev *sd,
1373 tc358743_print_register_map(sd);
1379 reg->val = i2c_rdreg(sd, reg->reg, reg->size);
1384 static int tc358743_s_register(struct v4l2_subdev *sd,
1388 tc358743_print_register_map(sd);
1405 i2c_wrreg(sd, (u16)reg->reg, reg->val,
1412 static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1414 u16 intstatus = i2c_rd16(sd, INTSTATUS);
1416 v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus);
1419 u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
1420 u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);
1423 tc358743_hdmi_misc_int_handler(sd, handled);
1425 tc358743_hdmi_cbit_int_handler(sd, handled);
1427 tc358743_hdmi_clk_int_handler(sd, handled);
1429 tc358743_hdmi_sys_int_handler(sd, handled);
1431 tc358743_hdmi_audio_int_handler(sd, handled);
1433 i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT);
1439 tc358743_cec_handler(sd, intstatus, handled);
1440 i2c_wr16(sd, INTSTATUS,
1447 u32 csi_int = i2c_rd32(sd, CSI_INT);
1450 tc358743_csi_err_int_handler(sd, handled);
1452 i2c_wr16(sd, INTSTATUS, MASK_CSI_INT);
1455 intstatus = i2c_rd16(sd, INTSTATUS);
1457 v4l2_dbg(1, debug, sd,
1470 tc358743_isr(&state->sd, 0, &handled);
1495 tc358743_isr(&state->sd, 0, &handled);
1498 static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1503 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
1505 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
1513 static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status)
1516 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1517 *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0;
1519 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1524 static int tc358743_s_dv_timings(struct v4l2_subdev *sd,
1527 struct tc358743_state *state = to_state(sd);
1533 v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ",
1537 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1543 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1549 enable_stream(sd, false);
1550 tc358743_set_pll(sd);
1551 tc358743_set_csi(sd);
1556 static int tc358743_g_dv_timings(struct v4l2_subdev *sd,
1559 struct tc358743_state *state = to_state(sd);
1566 static int tc358743_enum_dv_timings(struct v4l2_subdev *sd,
1576 static int tc358743_query_dv_timings(struct v4l2_subdev *sd,
1581 ret = tc358743_get_detected_timings(sd, timings);
1586 v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ",
1591 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1598 static int tc358743_dv_timings_cap(struct v4l2_subdev *sd,
1609 static int tc358743_get_mbus_config(struct v4l2_subdev *sd,
1613 struct tc358743_state *state = to_state(sd);
1624 static int tc358743_s_stream(struct v4l2_subdev *sd, int enable)
1626 enable_stream(sd, enable);
1629 tc358743_set_csi(sd);
1637 static int tc358743_enum_mbus_code(struct v4l2_subdev *sd,
1654 static int tc358743_get_fmt(struct v4l2_subdev *sd,
1658 struct tc358743_state *state = to_state(sd);
1659 u8 vi_rep = i2c_rd8(sd, VI_REP);
1690 static int tc358743_set_fmt(struct v4l2_subdev *sd,
1694 struct tc358743_state *state = to_state(sd);
1697 int ret = tc358743_get_fmt(sd, sd_state, format);
1717 enable_stream(sd, false);
1718 tc358743_set_pll(sd);
1719 tc358743_set_csi(sd);
1720 tc358743_set_csi_color_space(sd);
1725 static int tc358743_g_edid(struct v4l2_subdev *sd,
1728 struct tc358743_state *state = to_state(sd);
1750 i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid,
1756 static int tc358743_s_edid(struct v4l2_subdev *sd,
1759 struct tc358743_state *state = to_state(sd);
1765 v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n",
1787 tc358743_disable_edid(sd);
1789 i2c_wr8(sd, EDID_LEN1, edid_len & 0xff);
1790 i2c_wr8(sd, EDID_LEN2, edid_len >> 8);
1798 i2c_wr(sd, EDID_RAM + i, edid->edid + i, EDID_BLOCK_SIZE);
1804 if (tx_5v_power_present(sd))
1805 tc358743_enable_edid(sd);
2022 struct v4l2_subdev *sd;
2050 sd = &state->sd;
2051 v4l2_i2c_subdev_init(sd, client, &tc358743_ops);
2052 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
2055 if ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) {
2056 v4l2_info(sd, "not a TC358743 on address 0x%x\n",
2074 sd->ctrl_handler = &state->hdl;
2080 if (tc358743_update_controls(sd)) {
2086 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
2087 err = media_entity_pads_init(&sd->entity, 1, &state->pad);
2093 sd->dev = &client->dev;
2111 tc358743_initial_setup(sd);
2113 tc358743_s_dv_timings(sd, &default_timing);
2115 tc358743_set_csi_color_space(sd);
2117 tc358743_init_interrupts(sd);
2144 tc358743_enable_interrupts(sd, tx_5v_power_present(sd));
2145 i2c_wr16(sd, INTMASK, ~irq_mask);
2147 err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
2151 err = v4l2_async_register_subdev(sd);
2155 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2167 media_entity_cleanup(&sd->entity);
2174 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2175 struct tc358743_state *state = to_state(sd);
2183 v4l2_async_unregister_subdev(sd);
2184 v4l2_device_unregister_subdev(sd);
2186 media_entity_cleanup(&sd->entity);