Lines Matching refs:bridge
3 * Driver for ST MIPID02 CSI-2 to PARALLEL bridge
241 static int mipid02_read_reg(struct mipid02_dev *bridge, u16 reg, u8 *val)
243 struct i2c_client *client = bridge->i2c_client;
271 static int mipid02_write_reg(struct mipid02_dev *bridge, u16 reg, u8 val)
273 struct i2c_client *client = bridge->i2c_client;
297 static int mipid02_get_regulators(struct mipid02_dev *bridge)
302 bridge->supplies[i].supply = mipid02_supply_name[i];
304 return devm_regulator_bulk_get(&bridge->i2c_client->dev,
306 bridge->supplies);
309 static void mipid02_apply_reset(struct mipid02_dev *bridge)
311 gpiod_set_value_cansleep(bridge->reset_gpio, 0);
313 gpiod_set_value_cansleep(bridge->reset_gpio, 1);
315 gpiod_set_value_cansleep(bridge->reset_gpio, 0);
319 static int mipid02_set_power_on(struct mipid02_dev *bridge)
321 struct i2c_client *client = bridge->i2c_client;
324 ret = clk_prepare_enable(bridge->xclk);
331 bridge->supplies);
338 if (bridge->reset_gpio) {
340 mipid02_apply_reset(bridge);
349 clk_disable_unprepare(bridge->xclk);
353 static void mipid02_set_power_off(struct mipid02_dev *bridge)
355 regulator_bulk_disable(MIPID02_NUM_SUPPLIES, bridge->supplies);
356 clk_disable_unprepare(bridge->xclk);
359 static int mipid02_detect(struct mipid02_dev *bridge)
367 return mipid02_read_reg(bridge, MIPID02_CLK_LANE_WR_REG1, ®);
370 static u32 mipid02_get_link_freq_from_cid_link_freq(struct mipid02_dev *bridge,
389 static u32 mipid02_get_link_freq_from_cid_pixel_rate(struct mipid02_dev *bridge,
392 struct v4l2_fwnode_endpoint *ep = &bridge->rx;
395 u32 bpp = bpp_from_code(bridge->fmt.code);
410 static int mipid02_configure_from_rx_speed(struct mipid02_dev *bridge)
412 struct i2c_client *client = bridge->i2c_client;
413 struct v4l2_subdev *subdev = bridge->s_subdev;
416 link_freq = mipid02_get_link_freq_from_cid_link_freq(bridge, subdev);
418 link_freq = mipid02_get_link_freq_from_cid_pixel_rate(bridge,
427 bridge->r.clk_lane_reg1 |= (2000000000 / link_freq) << 2;
432 static int mipid02_configure_clk_lane(struct mipid02_dev *bridge)
434 struct i2c_client *client = bridge->i2c_client;
435 struct v4l2_fwnode_endpoint *ep = &bridge->rx;
443 bridge->r.clk_lane_reg1 |= (polarities[0] << 1) | CLK_ENABLE;
448 static int mipid02_configure_data0_lane(struct mipid02_dev *bridge, int nb,
461 bridge->r.data_lane0_reg1 = 1 << 1;
462 bridge->r.data_lane0_reg1 |= DATA_ENABLE;
467 static int mipid02_configure_data1_lane(struct mipid02_dev *bridge, int nb,
476 bridge->r.data_lane1_reg1 = 1 << 1;
477 bridge->r.data_lane1_reg1 |= DATA_ENABLE;
482 static int mipid02_configure_from_rx(struct mipid02_dev *bridge)
484 struct v4l2_fwnode_endpoint *ep = &bridge->rx;
490 ret = mipid02_configure_clk_lane(bridge);
494 ret = mipid02_configure_data0_lane(bridge, nb, are_lanes_swap,
499 ret = mipid02_configure_data1_lane(bridge, nb, are_lanes_swap,
504 bridge->r.mode_reg1 |= are_lanes_swap ? MODE_DATA_SWAP : 0;
505 bridge->r.mode_reg1 |= (nb - 1) << 1;
507 return mipid02_configure_from_rx_speed(bridge);
510 static int mipid02_configure_from_tx(struct mipid02_dev *bridge)
512 struct v4l2_fwnode_endpoint *ep = &bridge->tx;
514 bridge->r.data_selection_ctrl = SELECTION_MANUAL_WIDTH;
515 bridge->r.pix_width_ctrl = ep->bus.parallel.bus_width;
516 bridge->r.pix_width_ctrl_emb = ep->bus.parallel.bus_width;
518 bridge->r.mode_reg2 |= MODE_HSYNC_ACTIVE_HIGH;
520 bridge->r.mode_reg2 |= MODE_VSYNC_ACTIVE_HIGH;
522 bridge->r.mode_reg2 |= MODE_PCLK_SAMPLE_RISING;
527 static int mipid02_configure_from_code(struct mipid02_dev *bridge)
531 bridge->r.data_id_rreg = 0;
533 if (bridge->fmt.code != MEDIA_BUS_FMT_JPEG_1X8) {
534 bridge->r.data_selection_ctrl |= SELECTION_MANUAL_DATA;
536 data_type = data_type_from_code(bridge->fmt.code);
539 bridge->r.data_id_rreg = data_type;
545 static int mipid02_stream_disable(struct mipid02_dev *bridge)
547 struct i2c_client *client = bridge->i2c_client;
550 if (!bridge->s_subdev)
553 ret = v4l2_subdev_call(bridge->s_subdev, video, s_stream, 0);
558 ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG1, 0);
561 ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG1, 0);
564 ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG1, 0);
574 static int mipid02_stream_enable(struct mipid02_dev *bridge)
576 struct i2c_client *client = bridge->i2c_client;
579 if (!bridge->s_subdev)
582 memset(&bridge->r, 0, sizeof(bridge->r));
584 ret = mipid02_configure_from_rx(bridge);
587 ret = mipid02_configure_from_tx(bridge);
590 ret = mipid02_configure_from_code(bridge);
595 ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG1,
596 bridge->r.clk_lane_reg1);
599 ret = mipid02_write_reg(bridge, MIPID02_CLK_LANE_REG3, CLK_MIPI_CSI);
602 ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG1,
603 bridge->r.data_lane0_reg1);
606 ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE0_REG2,
610 ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG1,
611 bridge->r.data_lane1_reg1);
614 ret = mipid02_write_reg(bridge, MIPID02_DATA_LANE1_REG2,
618 ret = mipid02_write_reg(bridge, MIPID02_MODE_REG1,
619 MODE_NO_BYPASS | bridge->r.mode_reg1);
622 ret = mipid02_write_reg(bridge, MIPID02_MODE_REG2,
623 bridge->r.mode_reg2);
626 ret = mipid02_write_reg(bridge, MIPID02_DATA_ID_RREG,
627 bridge->r.data_id_rreg);
630 ret = mipid02_write_reg(bridge, MIPID02_DATA_SELECTION_CTRL,
631 bridge->r.data_selection_ctrl);
634 ret = mipid02_write_reg(bridge, MIPID02_PIX_WIDTH_CTRL,
635 bridge->r.pix_width_ctrl);
638 ret = mipid02_write_reg(bridge, MIPID02_PIX_WIDTH_CTRL_EMB,
639 bridge->r.pix_width_ctrl_emb);
643 ret = v4l2_subdev_call(bridge->s_subdev, video, s_stream, 1);
651 mipid02_stream_disable(bridge);
658 struct mipid02_dev *bridge = to_mipid02_dev(sd);
659 struct i2c_client *client = bridge->i2c_client;
663 enable, bridge->streaming);
664 mutex_lock(&bridge->lock);
666 if (bridge->streaming == enable)
669 ret = enable ? mipid02_stream_enable(bridge) :
670 mipid02_stream_disable(bridge);
672 bridge->streaming = enable;
676 bridge->streaming, ret);
677 mutex_unlock(&bridge->lock);
686 struct mipid02_dev *bridge = to_mipid02_dev(sd);
698 code->code = serial_to_parallel_code(bridge->fmt.code);
714 struct mipid02_dev *bridge = to_mipid02_dev(sd);
715 struct i2c_client *client = bridge->i2c_client;
727 fmt = v4l2_subdev_get_try_format(&bridge->sd, sd_state,
730 fmt = &bridge->fmt;
732 mutex_lock(&bridge->lock);
739 mutex_unlock(&bridge->lock);
748 struct mipid02_dev *bridge = to_mipid02_dev(sd);
752 format->format = bridge->fmt;
772 struct mipid02_dev *bridge = to_mipid02_dev(sd);
781 fmt = &bridge->fmt;
797 struct mipid02_dev *bridge = to_mipid02_dev(sd);
798 struct i2c_client *client = bridge->i2c_client;
809 mutex_lock(&bridge->lock);
811 if (bridge->streaming) {
822 mutex_unlock(&bridge->lock);
850 struct mipid02_dev *bridge = to_mipid02_dev(notifier->sd);
851 struct i2c_client *client = bridge->i2c_client;
867 &bridge->sd.entity, 0,
875 bridge->s_subdev = s_subdev;
884 struct mipid02_dev *bridge = to_mipid02_dev(notifier->sd);
886 bridge->s_subdev = NULL;
894 static int mipid02_parse_rx_ep(struct mipid02_dev *bridge)
897 struct i2c_client *client = bridge->i2c_client;
903 ep_node = of_graph_get_endpoint_by_regs(bridge->i2c_client->dev.of_node,
927 bridge->rx = ep;
930 v4l2_async_subdev_nf_init(&bridge->notifier, &bridge->sd);
931 asd = v4l2_async_nf_add_fwnode_remote(&bridge->notifier,
941 bridge->notifier.ops = &mipid02_notifier_ops;
943 ret = v4l2_async_nf_register(&bridge->notifier);
945 v4l2_async_nf_cleanup(&bridge->notifier);
956 static int mipid02_parse_tx_ep(struct mipid02_dev *bridge)
959 struct i2c_client *client = bridge->i2c_client;
964 ep_node = of_graph_get_endpoint_by_regs(bridge->i2c_client->dev.of_node,
979 bridge->tx = ep;
993 struct mipid02_dev *bridge;
997 bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
998 if (!bridge)
1001 init_format(&bridge->fmt);
1003 bridge->i2c_client = client;
1004 v4l2_i2c_subdev_init(&bridge->sd, client, &mipid02_subdev_ops);
1007 bridge->xclk = devm_clk_get(dev, "xclk");
1008 if (IS_ERR(bridge->xclk)) {
1010 return PTR_ERR(bridge->xclk);
1013 clk_freq = clk_get_rate(bridge->xclk);
1020 bridge->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1023 if (IS_ERR(bridge->reset_gpio)) {
1025 return PTR_ERR(bridge->reset_gpio);
1028 ret = mipid02_get_regulators(bridge);
1034 mutex_init(&bridge->lock);
1035 bridge->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1036 bridge->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
1037 bridge->sd.entity.ops = &mipid02_subdev_entity_ops;
1038 bridge->pad[0].flags = MEDIA_PAD_FL_SINK;
1039 bridge->pad[1].flags = MEDIA_PAD_FL_SINK;
1040 bridge->pad[2].flags = MEDIA_PAD_FL_SOURCE;
1041 ret = media_entity_pads_init(&bridge->sd.entity, MIPID02_PAD_NB,
1042 bridge->pad);
1049 ret = mipid02_set_power_on(bridge);
1053 ret = mipid02_detect(bridge);
1059 ret = mipid02_parse_tx_ep(bridge);
1065 ret = mipid02_parse_rx_ep(bridge);
1071 ret = v4l2_async_register_subdev(&bridge->sd);
1083 v4l2_async_nf_unregister(&bridge->notifier);
1084 v4l2_async_nf_cleanup(&bridge->notifier);
1086 mipid02_set_power_off(bridge);
1088 media_entity_cleanup(&bridge->sd.entity);
1090 mutex_destroy(&bridge->lock);
1098 struct mipid02_dev *bridge = to_mipid02_dev(sd);
1100 v4l2_async_nf_unregister(&bridge->notifier);
1101 v4l2_async_nf_cleanup(&bridge->notifier);
1102 v4l2_async_unregister_subdev(&bridge->sd);
1103 mipid02_set_power_off(bridge);
1104 media_entity_cleanup(&bridge->sd.entity);
1105 mutex_destroy(&bridge->lock);
1126 MODULE_DESCRIPTION("STMicroelectronics MIPID02 CSI-2 bridge driver");