Lines Matching defs:saa711x_write
109 static inline int saa711x_write(struct v4l2_subdev *sd, u8 reg, u8 value)
166 if (saa711x_write(sd, reg, data) < 0)
794 saa711x_write(sd, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03);
795 saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10 << state->double_asclk);
796 saa711x_write(sd, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc);
798 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff);
799 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+1,
801 saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+2,
804 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC, acni & 0xff);
805 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+1, (acni >> 8) & 0xff);
806 saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+2, (acni >> 16) & 0x3f);
834 saa711x_write(sd, R_0A_LUMA_BRIGHT_CNTL, ctrl->val);
838 saa711x_write(sd, R_0B_LUMA_CONTRAST_CNTL, ctrl->val);
842 saa711x_write(sd, R_0C_CHROMA_SAT_CNTL, ctrl->val);
846 saa711x_write(sd, R_0D_CHROMA_HUE_CNTL, ctrl->val);
852 saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val);
854 saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val | 0x80);
899 saa711x_write(sd, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,
901 saa711x_write(sd, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB,
912 saa711x_write(sd, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,
914 saa711x_write(sd, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB,
925 saa711x_write(sd, R_D0_B_HORIZ_PRESCALING,
930 saa711x_write(sd, R_D8_B_HORIZ_LUMA_SCALING_INC,
932 saa711x_write(sd, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB,
936 saa711x_write(sd, R_DC_B_HORIZ_CHROMA_SCALING,
938 saa711x_write(sd, R_DD_B_HORIZ_CHROMA_SCALING_MSB,
945 saa711x_write(sd, R_D5_B_LUMA_CONTRAST_CNTL,
947 saa711x_write(sd, R_D6_B_CHROMA_SATURATION_CNTL,
951 saa711x_write(sd, R_E0_B_VERT_LUMA_SCALING_INC,
953 saa711x_write(sd, R_E1_B_VERT_LUMA_SCALING_INC_MSB,
956 saa711x_write(sd, R_E2_B_VERT_CHROMA_SCALING_INC,
958 saa711x_write(sd, R_E3_B_VERT_CHROMA_SCALING_INC_MSB,
964 saa711x_write(sd, R_80_GLOBAL_CNTL_1,
993 saa711x_write(sd, R_08_SYNC_CNTL, reg);
1003 saa711x_write(sd, R_08_SYNC_CNTL, reg);
1034 saa711x_write(sd, R_0E_CHROMA_CNTL_1, reg);
1121 saa711x_write(sd, i - 2 + R_41_LCR_BASE, lcr[i]);
1316 saa711x_write(sd, R_10_CHROMA_CNTL_2,
1319 saa711x_write(sd, R_13_RT_X_PORT_OUT_CNTL,
1325 saa711x_write(sd, R_02_INPUT_CNTL_1,
1330 saa711x_write(sd, R_09_LUMA_CNTL,
1337 saa711x_write(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK,
1343 saa711x_write(sd, R_85_I_PORT_SIGNAL_POLAR, 0x20);
1345 saa711x_write(sd, R_85_I_PORT_SIGNAL_POLAR, 0x21);
1356 saa711x_write(sd, 0x11, (saa711x_read(sd, 0x11) & 0x7f) |
1373 saa711x_write(sd, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, state->enable);
1516 saa711x_write(sd, reg->reg & 0xff, reg->val & 0xff);
1645 saa711x_write(sd, R_08_SYNC_CNTL, work);
1653 saa711x_write(sd, R_10_CHROMA_CNTL_2, work);
1660 saa711x_write(sd, R_10_CHROMA_CNTL_2, work);
1671 saa711x_write(sd, R_12_RT_SIGNAL_CNTL, work);
1678 saa711x_write(sd, R_12_RT_SIGNAL_CNTL, work);
1686 saa711x_write(sd, R_13_RT_X_PORT_OUT_CNTL, work);