Lines Matching refs:config
1569 const struct ov8865_pll1_config *config;
1572 config = sensor->pll_configs->pll1_config;
1573 pll1_rate = sensor->extclk_rate * config->pll_mul / config->pll_pre_div_half;
1575 switch (config->pll_pre_div) {
1596 pll1_rate /= config->pll_pre_div;
1607 const struct ov8865_pll1_config *config;
1611 config = sensor->pll_configs->pll1_config;
1626 OV8865_PLL_CTRLA_PRE_DIV_HALF(config->pll_pre_div_half));
1631 OV8865_PLL_CTRL0_PRE_DIV(config->pll_pre_div));
1636 OV8865_PLL_CTRL1_MUL_H(config->pll_mul));
1641 OV8865_PLL_CTRL2_MUL_L(config->pll_mul));
1646 OV8865_PLL_CTRL3_M_DIV(config->m_div));
1651 OV8865_PLL_CTRL4_MIPI_DIV(config->mipi_div));
1657 OV8865_PCLK_SEL_PCLK_DIV(config->pclk_div));
1662 OV8865_PLL_CTRL5_SYS_PRE_DIV(config->sys_pre_div));
1667 OV8865_PLL_CTRL6_SYS_DIV(config->sys_div));
1679 const struct ov8865_pll2_config *config;
1682 config = mode->pll2_binning ? sensor->pll_configs->pll2_config_binning :
1686 OV8865_PLL_CTRL12_PRE_DIV_HALF(config->pll_pre_div_half) |
1687 OV8865_PLL_CTRL12_DAC_DIV(config->dac_div));
1692 OV8865_PLL_CTRLB_PRE_DIV(config->pll_pre_div));
1697 OV8865_PLL_CTRLC_MUL_H(config->pll_mul));
1702 OV8865_PLL_CTRLD_MUL_L(config->pll_mul));
1707 OV8865_PLL_CTRLF_SYS_PRE_DIV(config->sys_pre_div));
1712 OV8865_PLL_CTRLE_SYS_DIV(config->sys_div));
1718 const struct ov8865_sclk_config *config = &ov8865_sclk_config_native;
1722 OV8865_CLK_SEL0_PLL1_SYS_SEL(config->sys_sel));
1728 OV8865_CLK_SEL1_PLL_SCLK_SEL(config->sclk_sel));
1734 OV8865_SCLK_CTRL_SCLK_DIV(config->sclk_div) |
1735 OV8865_SCLK_CTRL_SCLK_PRE_DIV(config->sclk_pre_div));
2113 const struct ov8865_pll1_config *config;
2116 config = sensor->pll_configs->pll1_config;
2120 return pll1_rate / config->m_div / 2;
3042 dev_err_probe(dev, ret, "invalid clock config\n");