Lines Matching defs:pll_mul
491 * +-+ pll_mul (0x301 [1:0], 0x302 [7:0])
522 unsigned int pll_mul;
539 * +-+ pll_mul (0x30c [1:0], 0x30d [7:0])
565 unsigned int pll_mul;
719 .pll_mul = 75,
730 .pll_mul = 30,
746 .pll_mul = 75,
755 .pll_mul = 30,
769 .pll_mul = 75,
778 .pll_mul = 30,
1573 pll1_rate = sensor->extclk_rate * config->pll_mul / config->pll_pre_div_half;
1636 OV8865_PLL_CTRL1_MUL_H(config->pll_mul));
1641 OV8865_PLL_CTRL2_MUL_L(config->pll_mul));
1697 OV8865_PLL_CTRLC_MUL_H(config->pll_mul));
1702 OV8865_PLL_CTRLD_MUL_L(config->pll_mul));