Lines Matching defs:xvclk
90 struct clk *xvclk;
110 /* PLL settings bases on 24M xvclk */
458 ret = clk_prepare_enable(ov2685->xvclk);
460 dev_err(dev, "Failed to enable xvclk\n");
474 /* 8192 xvclk cycles prior to the first SCCB transaction */
492 clk_disable_unprepare(ov2685->xvclk);
499 /* 512 xvclk cycles after the last SCCB transaction or MIPI frame end */
503 clk_disable_unprepare(ov2685->xvclk);
797 ov2685->xvclk = devm_clk_get(dev, "xvclk");
798 if (IS_ERR(ov2685->xvclk)) {
799 dev_err(dev, "Failed to get xvclk\n");
802 ret = clk_set_rate(ov2685->xvclk, OV2685_XVCLK_FREQ);
804 dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
807 if (clk_get_rate(ov2685->xvclk) != OV2685_XVCLK_FREQ)
808 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");