Lines Matching refs:mt9v111
278 struct mt9v111_dev *mt9v111 = sd_to_mt9v111(sd);
282 if (mt9v111->addr_space == addr_space)
297 mt9v111->addr_space = addr_space;
363 struct mt9v111_dev *mt9v111 = sd_to_mt9v111(sd);
366 ret = clk_prepare_enable(mt9v111->clk);
370 clk_set_rate(mt9v111->clk, mt9v111->sysclk);
372 gpiod_set_value(mt9v111->standby, 0);
375 gpiod_set_value(mt9v111->oe, 1);
383 struct mt9v111_dev *mt9v111 = sd_to_mt9v111(sd);
385 gpiod_set_value(mt9v111->oe, 0);
388 gpiod_set_value(mt9v111->standby, 1);
391 clk_disable_unprepare(mt9v111->clk);
396 static int __mt9v111_hw_reset(struct mt9v111_dev *mt9v111)
398 if (!mt9v111->reset)
401 gpiod_set_value(mt9v111->reset, 1);
404 gpiod_set_value(mt9v111->reset, 0);
410 static int __mt9v111_sw_reset(struct mt9v111_dev *mt9v111)
412 struct i2c_client *c = mt9v111->client;
448 static int mt9v111_calc_frame_rate(struct mt9v111_dev *mt9v111,
493 pclk = DIV_ROUND_CLOSEST(mt9v111->sysclk, 2);
520 ret = v4l2_ctrl_s_ctrl_int64(mt9v111->hblank, hb);
524 ret = v4l2_ctrl_s_ctrl_int64(mt9v111->vblank, vb);
534 static int mt9v111_hw_config(struct mt9v111_dev *mt9v111)
536 struct i2c_client *c = mt9v111->client;
541 ret = __mt9v111_hw_reset(mt9v111);
543 ret = __mt9v111_sw_reset(mt9v111);
548 ret = mt9v111->sysclk < DIV_ROUND_CLOSEST(MT9V111_MAX_CLKIN, 2) ?
564 switch (mt9v111->fmt.code) {
620 mt9v111->fmt.width);
625 mt9v111->fmt.height);
630 ret = v4l2_ctrl_handler_setup(&mt9v111->ctrls);
648 struct mt9v111_dev *mt9v111 = sd_to_mt9v111(sd);
652 mutex_lock(&mt9v111->pwr_mutex);
658 pwr_count = mt9v111->pwr_count;
665 mt9v111->pwr_count = pwr_count;
667 mutex_unlock(&mt9v111->pwr_mutex);
677 mt9v111->pwr_count = pwr_count;
679 mutex_unlock(&mt9v111->pwr_mutex);
686 struct mt9v111_dev *mt9v111 = sd_to_mt9v111(subdev);
689 mutex_lock(&mt9v111->stream_mutex);
691 if (mt9v111->streaming == enable) {
692 mutex_unlock(&mt9v111->stream_mutex);
700 if (enable && mt9v111->pending) {
701 ret = mt9v111_hw_config(mt9v111);
710 mt9v111->pending = false;
713 mt9v111->streaming = enable ? true : false;
714 mutex_unlock(&mt9v111->stream_mutex);
719 mutex_unlock(&mt9v111->stream_mutex);
727 struct mt9v111_dev *mt9v111 = sd_to_mt9v111(sd);
737 mutex_lock(&mt9v111->stream_mutex);
739 if (mt9v111->streaming) {
740 mutex_unlock(&mt9v111->stream_mutex);
744 if (mt9v111->fps == fps) {
745 mutex_unlock(&mt9v111->stream_mutex);
750 if (mt9v111->fmt.width < QVGA_WIDTH &&
751 mt9v111->fmt.height < QVGA_HEIGHT)
753 else if (mt9v111->fmt.width < CIF_WIDTH &&
754 mt9v111->fmt.height < CIF_HEIGHT)
757 max_fps = mt9v111->sysclk <
762 mutex_unlock(&mt9v111->stream_mutex);
766 mt9v111_calc_frame_rate(mt9v111, tpf);
768 mt9v111->fps = fps;
769 mt9v111->pending = true;
771 mutex_unlock(&mt9v111->stream_mutex);
779 struct mt9v111_dev *mt9v111 = sd_to_mt9v111(sd);
782 mutex_lock(&mt9v111->stream_mutex);
785 tpf->denominator = mt9v111->fps;
787 mutex_unlock(&mt9v111->stream_mutex);
793 struct mt9v111_dev *mt9v111,
801 return v4l2_subdev_get_try_format(&mt9v111->sd, sd_state, pad);
806 return &mt9v111->fmt;
866 struct mt9v111_dev *mt9v111 = sd_to_mt9v111(subdev);
871 mutex_lock(&mt9v111->stream_mutex);
872 format->format = *__mt9v111_get_pad_format(mt9v111, sd_state,
875 mutex_unlock(&mt9v111->stream_mutex);
884 struct mt9v111_dev *mt9v111 = sd_to_mt9v111(subdev);
891 mutex_lock(&mt9v111->stream_mutex);
892 if (mt9v111->streaming) {
893 mutex_unlock(&mt9v111->stream_mutex);
898 mutex_unlock(&mt9v111->stream_mutex);
929 __fmt = __mt9v111_get_pad_format(mt9v111, sd_state, format->pad,
944 mt9v111->pending = true;
946 dev_dbg(mt9v111->dev, "%s: mbus_code: %x - (%ux%u)\n",
952 mutex_unlock(&mt9v111->stream_mutex);
999 struct mt9v111_dev *mt9v111 = container_of(ctrl->handler,
1004 mutex_lock(&mt9v111->pwr_mutex);
1009 if (!mt9v111->pwr_count) {
1010 mt9v111->pending = true;
1011 mutex_unlock(&mt9v111->pwr_mutex);
1014 mutex_unlock(&mt9v111->pwr_mutex);
1023 if (mt9v111->auto_exp->is_new || mt9v111->auto_awb->is_new) {
1024 if (mt9v111->auto_exp->val == V4L2_EXPOSURE_MANUAL &&
1025 mt9v111->auto_awb->val == V4L2_WHITE_BALANCE_MANUAL)
1026 ret = mt9v111_update(mt9v111->client, MT9V111_R01_IFP,
1031 ret = mt9v111_update(mt9v111->client, MT9V111_R01_IFP,
1042 ret = mt9v111_update(mt9v111->client, MT9V111_R01_IFP,
1049 ret = mt9v111_update(mt9v111->client, MT9V111_R01_IFP,
1056 ret = mt9v111_update(mt9v111->client, MT9V111_R01_CORE,
1059 mt9v111->hblank->val);
1062 ret = mt9v111_update(mt9v111->client, MT9V111_R01_CORE,
1065 mt9v111->vblank->val);
1076 static int mt9v111_chip_probe(struct mt9v111_dev *mt9v111)
1081 ret = __mt9v111_power_on(&mt9v111->sd);
1085 ret = mt9v111_read(mt9v111->client, MT9V111_R01_CORE,
1092 dev_err(mt9v111->dev,
1099 dev_dbg(mt9v111->dev, "Chip identified: 0x%2x%2x\n",
1103 __mt9v111_power_off(&mt9v111->sd);
1110 struct mt9v111_dev *mt9v111;
1114 mt9v111 = devm_kzalloc(&client->dev, sizeof(*mt9v111), GFP_KERNEL);
1115 if (!mt9v111)
1118 mt9v111->dev = &client->dev;
1119 mt9v111->client = client;
1121 mt9v111->clk = devm_clk_get(&client->dev, NULL);
1122 if (IS_ERR(mt9v111->clk))
1123 return PTR_ERR(mt9v111->clk);
1125 mt9v111->sysclk = clk_get_rate(mt9v111->clk);
1126 if (mt9v111->sysclk > MT9V111_MAX_CLKIN)
1129 mt9v111->oe = devm_gpiod_get_optional(&client->dev, "enable",
1131 if (IS_ERR(mt9v111->oe)) {
1133 PTR_ERR(mt9v111->oe));
1134 return PTR_ERR(mt9v111->oe);
1137 mt9v111->standby = devm_gpiod_get_optional(&client->dev, "standby",
1139 if (IS_ERR(mt9v111->standby)) {
1141 PTR_ERR(mt9v111->standby));
1142 return PTR_ERR(mt9v111->standby);
1145 mt9v111->reset = devm_gpiod_get_optional(&client->dev, "reset",
1147 if (IS_ERR(mt9v111->reset)) {
1149 PTR_ERR(mt9v111->reset));
1150 return PTR_ERR(mt9v111->reset);
1153 mutex_init(&mt9v111->pwr_mutex);
1154 mutex_init(&mt9v111->stream_mutex);
1156 v4l2_ctrl_handler_init(&mt9v111->ctrls, 5);
1158 mt9v111->auto_awb = v4l2_ctrl_new_std(&mt9v111->ctrls,
1163 mt9v111->auto_exp = v4l2_ctrl_new_std_menu(&mt9v111->ctrls,
1168 mt9v111->hblank = v4l2_ctrl_new_std(&mt9v111->ctrls, &mt9v111_ctrl_ops,
1173 mt9v111->vblank = v4l2_ctrl_new_std(&mt9v111->ctrls, &mt9v111_ctrl_ops,
1180 v4l2_ctrl_new_std(&mt9v111->ctrls, &mt9v111_ctrl_ops,
1182 DIV_ROUND_CLOSEST(mt9v111->sysclk, 2), 1,
1183 DIV_ROUND_CLOSEST(mt9v111->sysclk, 2));
1185 if (mt9v111->ctrls.error) {
1186 ret = mt9v111->ctrls.error;
1189 mt9v111->sd.ctrl_handler = &mt9v111->ctrls;
1192 mt9v111->fmt = mt9v111_def_fmt;
1195 mt9v111->fps = 15;
1197 tpf.denominator = mt9v111->fps;
1198 mt9v111_calc_frame_rate(mt9v111, &tpf);
1200 mt9v111->pwr_count = 0;
1201 mt9v111->addr_space = MT9V111_R01_IFP;
1202 mt9v111->pending = true;
1204 v4l2_i2c_subdev_init(&mt9v111->sd, client, &mt9v111_ops);
1207 mt9v111->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1208 mt9v111->sd.entity.ops = &mt9v111_subdev_entity_ops;
1209 mt9v111->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1211 mt9v111->pad.flags = MEDIA_PAD_FL_SOURCE;
1212 ret = media_entity_pads_init(&mt9v111->sd.entity, 1, &mt9v111->pad);
1217 ret = mt9v111_chip_probe(mt9v111);
1221 ret = v4l2_async_register_subdev(&mt9v111->sd);
1229 media_entity_cleanup(&mt9v111->sd.entity);
1233 v4l2_ctrl_handler_free(&mt9v111->ctrls);
1235 mutex_destroy(&mt9v111->pwr_mutex);
1236 mutex_destroy(&mt9v111->stream_mutex);
1244 struct mt9v111_dev *mt9v111 = sd_to_mt9v111(sd);
1252 v4l2_ctrl_handler_free(&mt9v111->ctrls);
1254 mutex_destroy(&mt9v111->pwr_mutex);
1255 mutex_destroy(&mt9v111->stream_mutex);
1259 { .compatible = "aptina,mt9v111", },
1265 .name = "mt9v111",