Lines Matching refs:CCI_REG8
36 #define IMX219_REG_MODE_SELECT CCI_REG8(0x0100)
40 #define IMX219_REG_CSI_LANE_MODE CCI_REG8(0x0114)
44 #define IMX219_REG_DPHY_CTRL CCI_REG8(0x0128)
52 #define IMX219_REG_ANALOG_GAIN CCI_REG8(0x0157)
98 #define IMX219_REG_X_ODD_INC_A CCI_REG8(0x0170)
99 #define IMX219_REG_Y_ODD_INC_A CCI_REG8(0x0171)
100 #define IMX219_REG_ORIENTATION CCI_REG8(0x0172)
111 #define IMX219_REG_VTPXCK_DIV CCI_REG8(0x0301)
112 #define IMX219_REG_VTSYCK_DIV CCI_REG8(0x0303)
113 #define IMX219_REG_PREPLLCK_VT_DIV CCI_REG8(0x0304)
114 #define IMX219_REG_PREPLLCK_OP_DIV CCI_REG8(0x0305)
116 #define IMX219_REG_OPPXCK_DIV CCI_REG8(0x0309)
117 #define IMX219_REG_OPSYCK_DIV CCI_REG8(0x030b)
191 { CCI_REG8(0x30eb), 0x0c },
192 { CCI_REG8(0x30eb), 0x05 },
193 { CCI_REG8(0x300a), 0xff },
194 { CCI_REG8(0x300b), 0xff },
195 { CCI_REG8(0x30eb), 0x05 },
196 { CCI_REG8(0x30eb), 0x09 },
208 { CCI_REG8(0x455e), 0x00 },
209 { CCI_REG8(0x471e), 0x4b },
210 { CCI_REG8(0x4767), 0x0f },
211 { CCI_REG8(0x4750), 0x14 },
212 { CCI_REG8(0x4540), 0x00 },
213 { CCI_REG8(0x47b4), 0x14 },
214 { CCI_REG8(0x4713), 0x30 },
215 { CCI_REG8(0x478b), 0x10 },
216 { CCI_REG8(0x478f), 0x10 },
217 { CCI_REG8(0x4793), 0x10 },
218 { CCI_REG8(0x4797), 0x0e },
219 { CCI_REG8(0x479b), 0x0e },