Lines Matching refs:nport
430 u8 nport; /* RX port number, and index in priv->rxport[] */
486 u8 nport; /* TX port number, and index in priv->txport[] */
679 static int ub960_rxport_select(struct ub960_data *priv, u8 nport)
686 if (priv->reg_current.rxport == nport)
690 (nport << 4) | BIT(nport));
693 nport, ret);
697 priv->reg_current.rxport = nport;
702 static int ub960_rxport_read(struct ub960_data *priv, u8 nport, u8 reg, u8 *val)
710 ret = ub960_rxport_select(priv, nport);
729 static int ub960_rxport_write(struct ub960_data *priv, u8 nport, u8 reg, u8 val)
736 ret = ub960_rxport_select(priv, nport);
751 static int ub960_rxport_update_bits(struct ub960_data *priv, u8 nport, u8 reg,
759 ret = ub960_rxport_select(priv, nport);
774 static int ub960_rxport_read16(struct ub960_data *priv, u8 nport, u8 reg,
783 ret = ub960_rxport_select(priv, nport);
802 static int ub960_txport_select(struct ub960_data *priv, u8 nport)
809 if (priv->reg_current.txport == nport)
813 (nport << 4) | BIT(nport));
816 nport, ret);
820 priv->reg_current.txport = nport;
825 static int ub960_txport_read(struct ub960_data *priv, u8 nport, u8 reg, u8 *val)
833 ret = ub960_txport_select(priv, nport);
852 static int ub960_txport_write(struct ub960_data *priv, u8 nport, u8 reg, u8 val)
859 ret = ub960_txport_select(priv, nport);
874 static int ub960_txport_update_bits(struct ub960_data *priv, u8 nport, u8 reg,
882 ret = ub960_txport_select(priv, nport);
1041 dev_err(dev, "rx%u: alias pool exhausted\n", rxport->nport);
1053 rxport->nport, client->addr, alias, reg_idx);
1073 rxport->nport, client->addr);
1081 dev_dbg(dev, "rx%u: client 0x%02x released at slot %u\n", rxport->nport,
1117 u8 nport)
1129 txport->nport = nport;
1134 dev_err(dev, "tx%u: failed to parse endpoint data\n", nport);
1155 dev_err(dev, "tx%u: invalid 'link-frequencies' value\n", nport);
1162 priv->txports[nport] = txport;
1174 static void ub960_csi_handle_events(struct ub960_data *priv, u8 nport)
1180 ret = ub960_txport_read(priv, nport, UB960_TR_CSI_TX_ISR, &csi_tx_isr);
1185 dev_warn(dev, "TX%u: CSI_SYNC_ERROR\n", nport);
1188 dev_warn(dev, "TX%u: CSI_PASS_ERROR\n", nport);
1197 unsigned int nport;
1200 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
1201 struct ub960_rxport *rxport = priv->rxports[nport];
1214 while (nport--) {
1215 struct ub960_rxport *rxport = priv->rxports[nport];
1228 unsigned int nport;
1230 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
1231 struct ub960_rxport *rxport = priv->rxports[nport];
1241 unsigned int nport)
1245 ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1, &v);
1246 ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2, &v);
1247 ub960_rxport_read(priv, nport, UB960_RR_CSI_RX_STS, &v);
1248 ub960_rxport_read(priv, nport, UB960_RR_BCC_STATUS, &v);
1250 ub960_rxport_read(priv, nport, UB960_RR_RX_PAR_ERR_HI, &v);
1251 ub960_rxport_read(priv, nport, UB960_RR_RX_PAR_ERR_LO, &v);
1253 ub960_rxport_read(priv, nport, UB960_RR_CSI_ERR_COUNTER, &v);
1258 unsigned int nport;
1260 for (nport = 0; nport < priv->hw_data->num_rxports; nport++)
1261 ub960_rxport_clear_errors(priv, nport);
1265 unsigned int nport, s8 *strobe_pos)
1271 ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
1277 ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
1283 ret = ub960_rxport_read(priv, nport, UB960_RR_SFILTER_STS_0, &v);
1289 ub960_rxport_read(priv, nport, UB960_RR_SFILTER_STS_1, &v);
1301 unsigned int nport, s8 strobe_pos)
1317 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
1320 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport),
1337 unsigned int nport, u8 *eq_level)
1342 ret = ub960_rxport_read(priv, nport, UB960_RR_AEQ_STATUS, &v);
1353 unsigned int nport, u8 eq_level)
1367 ub960_rxport_read(priv, nport, UB960_RR_AEQ_BYPASS, &v);
1375 ub960_rxport_write(priv, nport, UB960_RR_AEQ_BYPASS, v);
1379 unsigned int nport, u8 eq_min, u8 eq_max)
1381 ub960_rxport_write(priv, nport, UB960_RR_AEQ_MIN_MAX,
1386 ub960_rxport_update_bits(priv, nport, UB960_RR_AEQ_CTL2,
1391 static void ub960_rxport_config_eq(struct ub960_data *priv, unsigned int nport)
1393 struct ub960_rxport *rxport = priv->rxports[nport];
1415 ub960_rxport_set_strobe_pos(priv, nport, rxport->eq.strobe_pos);
1417 ub960_rxport_set_strobe_pos(priv, nport, 0);
1420 ub960_rxport_set_eq_level(priv, nport,
1424 ub960_rxport_update_bits(priv, nport, UB960_RR_AEQ_BYPASS,
1428 ub960_rxport_set_eq_range(priv, nport,
1433 ub960_rxport_update_bits(priv, nport, UB960_RR_AEQ_BYPASS,
1438 static int ub960_rxport_link_ok(struct ub960_data *priv, unsigned int nport,
1449 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1,
1459 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2,
1464 ret = ub960_rxport_read(priv, nport, UB960_RR_CSI_RX_STS, &csi_rx_sts);
1468 ret = ub960_rxport_read(priv, nport, UB960_RR_CSI_ERR_COUNTER,
1473 ret = ub960_rxport_read(priv, nport, UB960_RR_BCC_STATUS, &bcc_sts);
1477 ret = ub960_rxport_read16(priv, nport, UB960_RR_RX_PAR_ERR_HI,
1506 u8 nport;
1525 for_each_set_bit(nport, &port_mask,
1527 struct ub960_rxport *rxport = priv->rxports[nport];
1533 ret = ub960_rxport_link_ok(priv, nport, &ok);
1542 if (!ok || !(link_ok_mask & BIT(nport)))
1546 link_ok_mask |= BIT(nport);
1548 link_ok_mask &= ~BIT(nport);
1563 for_each_set_bit(nport, &port_mask, priv->hw_data->num_rxports) {
1564 struct ub960_rxport *rxport = priv->rxports[nport];
1571 if (!(link_ok_mask & BIT(nport))) {
1572 dev_dbg(dev, "\trx%u: not locked\n", nport);
1576 ub960_rxport_read16(priv, nport, UB960_RR_RX_FREQ_HIGH, &v);
1578 ret = ub960_rxport_get_strobe_pos(priv, nport, &strobe_pos);
1582 ret = ub960_rxport_get_eq_level(priv, nport, &eq_level);
1587 nport, strobe_pos, eq_level, (v * 1000000ULL) >> 8);
1644 static int ub960_rxport_add_serializer(struct ub960_data *priv, u8 nport)
1646 struct ub960_rxport *rxport = priv->rxports[nport];
1655 ser_pdata->port = nport;
1671 dev_err(dev, "rx%u: cannot add %s i2c device", nport,
1677 nport, rxport->ser.client->addr,
1683 static void ub960_rxport_remove_serializer(struct ub960_data *priv, u8 nport)
1685 struct ub960_rxport *rxport = priv->rxports[nport];
1694 unsigned int nport;
1697 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
1698 struct ub960_rxport *rxport = priv->rxports[nport];
1703 ret = ub960_rxport_add_serializer(priv, nport);
1711 while (nport--) {
1712 struct ub960_rxport *rxport = priv->rxports[nport];
1717 ub960_rxport_remove_serializer(priv, nport);
1725 unsigned int nport;
1727 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
1728 struct ub960_rxport *rxport = priv->rxports[nport];
1733 ub960_rxport_remove_serializer(priv, nport);
1740 unsigned int nport = txport->nport;
1755 ub960_txport_write(priv, nport, UB960_TR_CSI_CTL, csi_ctl);
1760 unsigned int nport;
1808 for (nport = 0; nport < priv->hw_data->num_txports; nport++) {
1809 struct ub960_txport *txport = priv->txports[nport];
1823 unsigned int nport = rxport->nport;
1856 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
1863 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG,
1870 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2,
1884 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG, 0x3,
1891 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2, 0x3,
1895 ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_HI, 0x07);
1896 ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_LO, 0x7f);
1899 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
1904 ub960_rxport_write(priv, nport, UB960_RR_SER_ALIAS_ID,
1908 ub960_rxport_config_eq(priv, nport);
1911 ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, BIT(nport), BIT(nport));
1917 unsigned int nport = rxport->nport;
1951 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, 0x7,
1953 ub960_rxport_write(priv, nport, UB960_RR_CHANNEL_MODE, fpd_func_mode);
1956 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0xa8, 0x80);
1959 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x0d, 0x7f);
1962 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2b, 0x04);
1965 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0xa9, 0x23);
1968 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0xaa, 0);
1971 ub960_ind_update_bits(priv, UB960_IND_TARGET_RX_ANA(nport), 0x1b,
1975 ub960_update_bits(priv, UB960_SR_FPD_RATE_CFG, 0x3 << (nport * 2),
1976 BIT(nport * 2));
1982 unsigned int nport = rxport->nport;
1989 ub960_read_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2c, &v);
1991 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x27, v);
1992 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x28, v + 1);
1994 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2b, 0x00);
1998 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x9e, 0x00);
2001 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x90, 0x40);
2004 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2e, 0x40);
2007 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0xf0, 0x00);
2010 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x71, 0x00);
2016 unsigned int nport = rxport->nport;
2044 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG, 0x7,
2048 ub960_rxport_write(priv, nport, UB960_RR_CHANNEL_MODE, 0);
2051 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x2b, 0x04);
2054 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x27, 0x0);
2056 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x28, 0x23);
2059 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x04, 0x00);
2061 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x1b, 0x00);
2064 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x21, 0x2f);
2066 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x25, 0xc1);
2069 ub960_update_bits(priv, UB960_SR_FPD_RATE_CFG, 0x3 << (nport * 2),
2070 0 << (nport * 2));
2078 unsigned int nport = rxport->nport;
2091 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2,
2108 ub960_rxport_update_bits(priv, nport, UB960_RR_PORT_CONFIG2, 0x3,
2112 ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_HI, 0x07);
2113 ub960_rxport_write(priv, nport, UB960_RR_PORT_ICR_LO, 0x7f);
2116 ub960_rxport_update_bits(priv, nport, UB960_RR_BCC_CONFIG,
2121 ub960_rxport_write(priv, nport, UB960_RR_SER_ALIAS_ID,
2125 ub960_update_bits(priv, UB960_SR_RX_PORT_CTL, BIT(nport), BIT(nport));
2129 ub960_write_ind(priv, UB960_IND_TARGET_RX_ANA(nport), 0x25, 0x41);
2135 unsigned int nport;
2137 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2138 struct ub960_rxport *rxport = priv->rxports[nport];
2152 static void ub960_rxport_handle_events(struct ub960_data *priv, u8 nport)
2163 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1,
2166 ret = ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2,
2169 ret = ub960_rxport_read(priv, nport, UB960_RR_CSI_RX_STS,
2172 ret = ub960_rxport_read(priv, nport, UB960_RR_BCC_STATUS,
2181 ret = ub960_rxport_read16(priv, nport, UB960_RR_RX_PAR_ERR_HI,
2184 dev_err(dev, "rx%u parity errors: %u\n", nport, v);
2188 dev_err(dev, "rx%u BCC CRC error\n", nport);
2191 dev_err(dev, "rx%u BCC SEQ error\n", nport);
2194 dev_err(dev, "rx%u line length unstable\n", nport);
2197 dev_err(dev, "rx%u FPD3 encode error\n", nport);
2200 dev_err(dev, "rx%u buffer error\n", nport);
2203 dev_err(dev, "rx%u CSI error: %#02x\n", nport, csi_rx_sts);
2206 dev_err(dev, "rx%u CSI ECC1 error\n", nport);
2209 dev_err(dev, "rx%u CSI ECC2 error\n", nport);
2212 dev_err(dev, "rx%u CSI checksum error\n", nport);
2215 dev_err(dev, "rx%u CSI length error\n", nport);
2218 dev_err(dev, "rx%u BCC error: %#02x\n", nport, bcc_sts);
2221 dev_err(dev, "rx%u BCC response error", nport);
2224 dev_err(dev, "rx%u BCC slave timeout", nport);
2227 dev_err(dev, "rx%u BCC slave error", nport);
2230 dev_err(dev, "rx%u BCC master timeout", nport);
2233 dev_err(dev, "rx%u BCC master error", nport);
2236 dev_err(dev, "rx%u BCC sequence error", nport);
2241 ret = ub960_rxport_read16(priv, nport, UB960_RR_LINE_LEN_1, &v);
2243 dev_dbg(dev, "rx%u line len changed: %u\n", nport, v);
2249 ret = ub960_rxport_read16(priv, nport, UB960_RR_LINE_COUNT_HI,
2252 dev_dbg(dev, "rx%u line count changed: %u\n", nport, v);
2256 dev_dbg(dev, "rx%u: %s, %s, %s, %s\n", nport,
2314 static int ub960_enable_tx_port(struct ub960_data *priv, unsigned int nport)
2318 dev_dbg(dev, "enable TX port %u\n", nport);
2320 return ub960_txport_update_bits(priv, nport, UB960_TR_CSI_CTL,
2325 static void ub960_disable_tx_port(struct ub960_data *priv, unsigned int nport)
2329 dev_dbg(dev, "disable TX port %u\n", nport);
2331 ub960_txport_update_bits(priv, nport, UB960_TR_CSI_CTL,
2335 static int ub960_enable_rx_port(struct ub960_data *priv, unsigned int nport)
2339 dev_dbg(dev, "enable RX port %u\n", nport);
2343 UB960_SR_FWD_CTL1_PORT_DIS(nport), 0);
2346 static void ub960_disable_rx_port(struct ub960_data *priv, unsigned int nport)
2350 dev_dbg(dev, "disable RX port %u\n", nport);
2354 UB960_SR_FWD_CTL1_PORT_DIS(nport),
2355 UB960_SR_FWD_CTL1_PORT_DIS(nport));
2364 unsigned int nport;
2367 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2368 struct ub960_rxport *rxport = priv->rxports[nport];
2395 nport);
2416 unsigned int nport;
2430 unsigned int nport;
2432 nport = ub960_pad_to_port(priv, route->sink_pad);
2434 rxport = priv->rxports[nport];
2442 rx_data[nport].tx_port = ub960_pad_to_port(priv, route->source_pad);
2444 rx_data[nport].num_streams++;
2451 if (rx_data[nport].num_streams > 2)
2468 nport, fmt->height);
2472 rx_data[nport].meta_dt = ub960_fmt->datatype;
2473 rx_data[nport].meta_lines = fmt->height;
2475 rx_data[nport].pixel_dt = ub960_fmt->datatype;
2487 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2488 struct ub960_rxport *rxport = priv->rxports[nport];
2489 u8 vc = vc_map[nport];
2491 if (rx_data[nport].num_streams == 0)
2496 ub960_rxport_write(priv, nport, UB960_RR_RAW10_ID,
2497 rx_data[nport].pixel_dt | (vc << UB960_RR_RAW10_ID_VC_SHIFT));
2499 ub960_rxport_write(priv, rxport->nport,
2501 (rx_data[nport].meta_lines << UB960_RR_RAW_EMBED_DTYPE_LINES_SHIFT) |
2502 rx_data[nport].meta_dt);
2515 ub960_rxport_write(priv, nport, UB960_RR_CSI_VC_MAP,
2523 /* Map all VCs from this port to VC(nport) */
2525 ub960_rxport_write(priv, nport,
2527 nport);
2533 if (rx_data[nport].tx_port == 1)
2534 fwd_ctl |= BIT(nport); /* forward to TX1 */
2536 fwd_ctl &= ~BIT(nport); /* forward to TX0 */
2565 unsigned int nport;
2593 nport = ub960_pad_to_port(priv, route->sink_pad);
2595 sink_streams[nport] |= BIT_ULL(route->sink_stream);
2598 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2599 if (!sink_streams[nport])
2603 if (!priv->stream_enable_mask[nport]) {
2604 ret = ub960_enable_rx_port(priv, nport);
2606 failed_port = nport;
2611 priv->stream_enable_mask[nport] |= sink_streams[nport];
2613 dev_dbg(dev, "enable RX port %u streams %#llx\n", nport,
2614 sink_streams[nport]);
2617 priv->rxports[nport]->source.sd,
2618 priv->rxports[nport]->source.pad,
2619 sink_streams[nport]);
2621 priv->stream_enable_mask[nport] &= ~sink_streams[nport];
2623 if (!priv->stream_enable_mask[nport])
2624 ub960_disable_rx_port(priv, nport);
2626 failed_port = nport;
2636 for (nport = 0; nport < failed_port; nport++) {
2637 if (!sink_streams[nport])
2640 dev_dbg(dev, "disable RX port %u streams %#llx\n", nport,
2641 sink_streams[nport]);
2644 priv->rxports[nport]->source.sd,
2645 priv->rxports[nport]->source.pad,
2646 sink_streams[nport]);
2650 priv->stream_enable_mask[nport] &= ~sink_streams[nport];
2653 if (!priv->stream_enable_mask[nport])
2654 ub960_disable_rx_port(priv, nport);
2676 unsigned int nport;
2687 nport = ub960_pad_to_port(priv, route->sink_pad);
2689 sink_streams[nport] |= BIT_ULL(route->sink_stream);
2692 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2693 if (!sink_streams[nport])
2696 dev_dbg(dev, "disable RX port %u streams %#llx\n", nport,
2697 sink_streams[nport]);
2700 priv->rxports[nport]->source.sd,
2701 priv->rxports[nport]->source.pad,
2702 sink_streams[nport]);
2706 priv->stream_enable_mask[nport] &= ~sink_streams[nport];
2709 if (!priv->stream_enable_mask[nport])
2710 ub960_disable_rx_port(priv, nport);
2800 unsigned int nport;
2806 nport = ub960_pad_to_port(priv, route->sink_pad);
2808 ret = v4l2_subdev_call(priv->rxports[nport]->source.sd, pad,
2810 priv->rxports[nport]->source.pad,
2838 fd->entry[fd->num_entries].bus.csi2.vc = vc_map[nport];
2954 unsigned int nport;
2967 for (nport = 0; nport < priv->hw_data->num_txports; nport++) {
2968 struct ub960_txport *txport = priv->txports[nport];
2970 dev_info(dev, "TX %u\n", nport);
2977 ub960_txport_read(priv, nport, UB960_TR_CSI_STS, &v);
2981 ub960_read16(priv, UB960_SR_CSI_FRAME_COUNT_HI(nport), &v16);
2984 ub960_read16(priv, UB960_SR_CSI_FRAME_ERR_COUNT_HI(nport), &v16);
2987 ub960_read16(priv, UB960_SR_CSI_LINE_COUNT_HI(nport), &v16);
2990 ub960_read16(priv, UB960_SR_CSI_LINE_ERR_COUNT_HI(nport), &v16);
2994 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
2995 struct ub960_rxport *rxport = priv->rxports[nport];
3000 dev_info(dev, "RX %u\n", nport);
3007 ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS1, &v);
3015 ub960_rxport_read(priv, nport, UB960_RR_RX_PORT_STS2, &v);
3018 ub960_rxport_read16(priv, nport, UB960_RR_RX_FREQ_HIGH, &v16);
3021 ub960_rxport_read16(priv, nport, UB960_RR_RX_PAR_ERR_HI, &v16);
3024 ub960_rxport_read16(priv, nport, UB960_RR_LINE_COUNT_HI, &v16);
3027 ub960_rxport_read16(priv, nport, UB960_RR_LINE_LEN_1, &v16);
3030 ub960_rxport_read(priv, nport, UB960_RR_CSI_ERR_COUNTER, &v);
3049 ub960_rxport_get_strobe_pos(priv, nport, &strobe_pos);
3055 ub960_rxport_read(priv, nport, UB960_RR_AEQ_BYPASS, &v);
3062 ub960_rxport_read(priv, nport, UB960_RR_AEQ_MIN_MAX, &v);
3069 if (ub960_rxport_get_eq_level(priv, nport, &eq_level) == 0)
3080 ub960_rxport_read(priv, nport, ctl_reg, &v);
3163 unsigned int nport;
3165 for (nport = 0; nport < priv->hw_data->num_txports; nport++) {
3166 struct ub960_txport *txport = priv->txports[nport];
3172 priv->txports[nport] = NULL;
3178 unsigned int nport;
3180 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
3181 struct ub960_rxport *rxport = priv->rxports[nport];
3190 priv->rxports[nport] = NULL;
3200 unsigned int nport = rxport->nport;
3212 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
3218 dev_err(dev, "rx%u: bad 'ti,cdr-mode' %u\n", nport, cdr_mode);
3223 dev_err(dev, "rx%u: FPD-Link 4 CDR not supported\n", nport);
3231 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
3237 dev_err(dev, "rx%u: bad 'ti,rx-mode' %u\n", nport, rx_mode);
3244 dev_err(dev, "rx%u: unsupported 'ti,rx-mode' %u\n", nport,
3264 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
3272 nport, strobe_pos);
3281 nport);
3287 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
3294 nport, eq_level);
3305 dev_err(dev, "rx%u: failed to read '%s': %d\n", nport,
3313 dev_err(dev, "rx%u: missing 'serializer' node\n", nport);
3326 unsigned int nport = rxport->nport;
3333 dev_err(dev, "rx%u: no remote endpoint\n", nport);
3351 dev_err(dev, "rx%u: failed to parse endpoint data\n", nport);
3369 static int ub960_parse_dt_rxport(struct ub960_data *priv, unsigned int nport,
3384 priv->rxports[nport] = rxport;
3386 rxport->nport = nport;
3393 rxport->vpoc = devm_regulator_get_optional(dev, vpoc_names[nport]);
3400 nport, ret);
3414 priv->rxports[nport] = NULL;
3421 unsigned int nport)
3438 if (nport == link_num)
3449 unsigned int nport;
3464 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
3468 link_fwnode = ub960_fwnode_get_link_by_regs(links_fwnode, nport);
3473 nport, 0, 0);
3479 ret = ub960_parse_dt_rxport(priv, nport, link_fwnode,
3486 dev_err(dev, "rx%u: failed to parse RX port\n", nport);
3504 u32 nport;
3507 for (nport = 0; nport < priv->hw_data->num_txports; nport++) {
3508 unsigned int port = nport + priv->hw_data->num_rxports;
3516 ret = ub960_parse_dt_txport(priv, ep_fwnode, nport);
3554 u8 nport = rxport->nport;
3570 rxport->source.pad, &priv->sd.entity, nport,
3576 priv->sd.name, nport);
3887 unsigned int nport;
3938 for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
3939 struct ub960_rxport *rxport = priv->rxports[nport];
3944 port_mask |= BIT(nport);