Lines Matching refs:sd
90 struct v4l2_subdev sd;
249 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)
251 return container_of(sd, struct adv7842_state, sd);
256 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;
340 static inline int io_read(struct v4l2_subdev *sd, u8 reg)
342 struct i2c_client *client = v4l2_get_subdevdata(sd);
347 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
349 struct i2c_client *client = v4l2_get_subdevdata(sd);
354 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
356 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
359 static inline int io_write_clr_set(struct v4l2_subdev *sd,
362 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
365 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
367 struct adv7842_state *state = to_state(sd);
372 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
374 struct adv7842_state *state = to_state(sd);
379 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
381 struct adv7842_state *state = to_state(sd);
386 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
388 struct adv7842_state *state = to_state(sd);
393 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
395 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
398 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
400 struct adv7842_state *state = to_state(sd);
405 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
407 struct adv7842_state *state = to_state(sd);
412 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)
414 struct adv7842_state *state = to_state(sd);
419 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
421 struct adv7842_state *state = to_state(sd);
426 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
428 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);
431 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)
433 struct adv7842_state *state = to_state(sd);
438 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
440 struct adv7842_state *state = to_state(sd);
445 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
447 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);
450 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
452 struct adv7842_state *state = to_state(sd);
457 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
459 struct adv7842_state *state = to_state(sd);
464 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
466 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);
469 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
471 struct adv7842_state *state = to_state(sd);
476 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
478 struct adv7842_state *state = to_state(sd);
483 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
485 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
488 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
490 struct adv7842_state *state = to_state(sd);
495 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
497 struct adv7842_state *state = to_state(sd);
502 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
504 struct adv7842_state *state = to_state(sd);
509 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
511 struct adv7842_state *state = to_state(sd);
516 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
518 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
521 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
523 struct adv7842_state *state = to_state(sd);
528 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
530 struct adv7842_state *state = to_state(sd);
535 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
537 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
540 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
542 struct adv7842_state *state = to_state(sd);
547 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
549 struct adv7842_state *state = to_state(sd);
554 static void main_reset(struct v4l2_subdev *sd)
556 struct i2c_client *client = v4l2_get_subdevdata(sd);
558 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
625 static inline bool is_analog_input(struct v4l2_subdev *sd)
627 struct adv7842_state *state = to_state(sd);
633 static inline bool is_digital_input(struct v4l2_subdev *sd)
635 struct adv7842_state *state = to_state(sd);
663 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)
665 return is_digital_input(sd) ? &adv7842_timings_cap_digital :
671 static u16 adv7842_read_cable_det(struct v4l2_subdev *sd)
673 u8 reg = io_read(sd, 0x6f);
688 struct v4l2_subdev *sd = &state->sd;
692 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",
699 io_write_and_or(sd, 0x20, 0xcf, mask);
702 static int edid_write_vga_segment(struct v4l2_subdev *sd)
704 struct i2c_client *client = v4l2_get_subdevdata(sd);
705 struct adv7842_state *state = to_state(sd);
711 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);
717 io_write_and_or(sd, 0x20, 0xcf, 0x00);
720 rep_write_and_or(sd, 0x7f, 0x7f, 0x00);
723 rep_write_and_or(sd, 0x77, 0xef, 0x10);
735 rep_write_and_or(sd, 0x7f, 0x7f, 0x80);
738 if (rep_read(sd, 0x79) & 0x20)
753 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)
755 struct i2c_client *client = v4l2_get_subdevdata(sd);
756 struct adv7842_state *state = to_state(sd);
764 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c\n",
768 io_write_and_or(sd, 0x20, 0xcf, 0x00);
771 rep_write_and_or(sd, 0x77, 0xf3, 0x00);
796 rep_write_and_or(sd, 0x77, 0xef, i >= 256 ? 0x10 : 0x00);
804 rep_write(sd, 0x72, pa >> 8);
805 rep_write(sd, 0x73, pa & 0xff);
807 rep_write(sd, 0x74, pa >> 8);
808 rep_write(sd, 0x75, pa & 0xff);
810 rep_write(sd, 0x76, spa_loc & 0xff);
811 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
816 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);
819 if (rep_read(sd, 0x7d) & state->hdmi_edid.present)
839 static void adv7842_inv_register(struct v4l2_subdev *sd)
841 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
842 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
843 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
844 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
845 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");
846 v4l2_info(sd, "0x500-0x5ff: SDP Map\n");
847 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
848 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
849 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
850 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
851 v4l2_info(sd, "0xa00-0xaff: CP Map\n");
852 v4l2_info(sd, "0xb00-0xbff: VDP Map\n");
855 static int adv7842_g_register(struct v4l2_subdev *sd,
861 reg->val = io_read(sd, reg->reg & 0xff);
864 reg->val = avlink_read(sd, reg->reg & 0xff);
867 reg->val = cec_read(sd, reg->reg & 0xff);
870 reg->val = infoframe_read(sd, reg->reg & 0xff);
873 reg->val = sdp_io_read(sd, reg->reg & 0xff);
876 reg->val = sdp_read(sd, reg->reg & 0xff);
879 reg->val = afe_read(sd, reg->reg & 0xff);
882 reg->val = rep_read(sd, reg->reg & 0xff);
885 reg->val = edid_read(sd, reg->reg & 0xff);
888 reg->val = hdmi_read(sd, reg->reg & 0xff);
891 reg->val = cp_read(sd, reg->reg & 0xff);
894 reg->val = vdp_read(sd, reg->reg & 0xff);
897 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
898 adv7842_inv_register(sd);
904 static int adv7842_s_register(struct v4l2_subdev *sd,
911 io_write(sd, reg->reg & 0xff, val);
914 avlink_write(sd, reg->reg & 0xff, val);
917 cec_write(sd, reg->reg & 0xff, val);
920 infoframe_write(sd, reg->reg & 0xff, val);
923 sdp_io_write(sd, reg->reg & 0xff, val);
926 sdp_write(sd, reg->reg & 0xff, val);
929 afe_write(sd, reg->reg & 0xff, val);
932 rep_write(sd, reg->reg & 0xff, val);
935 edid_write(sd, reg->reg & 0xff, val);
938 hdmi_write(sd, reg->reg & 0xff, val);
941 cp_write(sd, reg->reg & 0xff, val);
944 vdp_write(sd, reg->reg & 0xff, val);
947 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
948 adv7842_inv_register(sd);
955 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
957 struct adv7842_state *state = to_state(sd);
958 u16 cable_det = adv7842_read_cable_det(sd);
960 v4l2_dbg(1, debug, sd, "%s: 0x%x\n", __func__, cable_det);
965 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
974 is_digital_input(sd) ? 250000 : 1000000, false))
977 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
979 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);
986 static int configure_predefined_video_timings(struct v4l2_subdev *sd,
989 struct adv7842_state *state = to_state(sd);
992 v4l2_dbg(1, debug, sd, "%s\n", __func__);
995 io_write(sd, 0x16, 0x43);
996 io_write(sd, 0x17, 0x5a);
998 cp_write_and_or(sd, 0x81, 0xef, 0x00);
999 cp_write(sd, 0x26, 0x00);
1000 cp_write(sd, 0x27, 0x00);
1001 cp_write(sd, 0x28, 0x00);
1002 cp_write(sd, 0x29, 0x00);
1003 cp_write(sd, 0x8f, 0x40);
1004 cp_write(sd, 0x90, 0x00);
1005 cp_write(sd, 0xa5, 0x00);
1006 cp_write(sd, 0xa6, 0x00);
1007 cp_write(sd, 0xa7, 0x00);
1008 cp_write(sd, 0xab, 0x00);
1009 cp_write(sd, 0xac, 0x00);
1014 err = find_and_set_predefined_video_timings(sd,
1017 err = find_and_set_predefined_video_timings(sd,
1021 err = find_and_set_predefined_video_timings(sd,
1024 err = find_and_set_predefined_video_timings(sd,
1028 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1038 static void configure_custom_video_timings(struct v4l2_subdev *sd,
1041 struct adv7842_state *state = to_state(sd);
1042 struct i2c_client *client = v4l2_get_subdevdata(sd);
1056 v4l2_dbg(2, debug, sd, "%s\n", __func__);
1062 io_write(sd, 0x00, 0x07); /* video std */
1063 io_write(sd, 0x01, 0x02); /* prim mode */
1065 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1071 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1076 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);
1077 cp_write(sd, 0x27, (cp_start_sav & 0xff));
1078 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);
1079 cp_write(sd, 0x29, (cp_start_eav & 0xff));
1082 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1083 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1085 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1090 io_write(sd, 0x00, 0x02); /* video std */
1091 io_write(sd, 0x01, 0x06); /* prim mode */
1094 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1099 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1100 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1101 cp_write(sd, 0xab, (height >> 4) & 0xff);
1102 cp_write(sd, 0xac, (height & 0x0f) << 4);
1105 static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1107 struct adv7842_state *state = to_state(sd);
1116 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1120 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1127 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1130 static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1132 struct adv7842_state *state = to_state(sd);
1145 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1156 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1159 static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1161 struct adv7842_state *state = to_state(sd);
1162 bool rgb_output = io_read(sd, 0x02) & 0x02;
1163 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1166 if (hdmi_signal && (io_read(sd, 0x60) & 1))
1167 y = infoframe_read(sd, 0x01) >> 5;
1169 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1173 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0);
1174 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0);
1175 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);
1182 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1189 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1196 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1205 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1208 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1210 if (is_digital_input(sd) && rgb_output) {
1211 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1213 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1214 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1221 io_write_and_or(sd, 0x02, 0x0f, 0x20);
1229 io_write_and_or(sd, 0x02, 0x0f, 0x00);
1235 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1243 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1245 if (is_analog_input(sd) || hdmi_signal)
1250 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);
1252 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1253 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);
1261 struct v4l2_subdev *sd = to_sd(ctrl);
1262 struct adv7842_state *state = to_state(sd);
1271 cp_write(sd, 0x3c, ctrl->val);
1272 sdp_write(sd, 0x14, ctrl->val);
1276 cp_write(sd, 0x3a, ctrl->val);
1277 sdp_write(sd, 0x13, ctrl->val);
1281 cp_write(sd, 0x3b, ctrl->val);
1282 sdp_write(sd, 0x15, ctrl->val);
1286 cp_write(sd, 0x3d, ctrl->val);
1287 sdp_write(sd, 0x16, ctrl->val);
1292 afe_write(sd, 0xc8, ctrl->val);
1295 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
1296 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));
1316 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);
1317 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);
1320 cp_write(sd, 0xc1, R);
1321 cp_write(sd, 0xc0, G);
1322 cp_write(sd, 0xc2, B);
1324 sdp_write(sd, 0xde, Y);
1325 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));
1330 set_rgb_quantization_range(sd);
1338 struct v4l2_subdev *sd = to_sd(ctrl);
1342 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1343 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1349 static inline bool no_power(struct v4l2_subdev *sd)
1351 return io_read(sd, 0x0c) & 0x24;
1354 static inline bool no_cp_signal(struct v4l2_subdev *sd)
1356 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);
1359 static inline bool is_hdmi(struct v4l2_subdev *sd)
1361 return hdmi_read(sd, 0x05) & 0x80;
1364 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)
1366 struct adv7842_state *state = to_state(sd);
1370 if (io_read(sd, 0x0c) & 0x24)
1375 if (!(sdp_read(sd, 0x5A) & 0x01))
1378 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",
1383 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||
1384 !(cp_read(sd, 0xb1) & 0x80))
1388 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))
1391 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",
1403 static int stdi2dv_timings(struct v4l2_subdev *sd,
1407 struct adv7842_state *state = to_state(sd);
1416 adv7842_get_dv_timings_cap(sd),
1444 v4l2_dbg(2, debug, sd,
1451 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1455 adv7842_g_input_status(sd, &status);
1457 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);
1461 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1462 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1463 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1465 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {
1466 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1467 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1468 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1469 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1474 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;
1477 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1481 v4l2_dbg(2, debug, sd,
1490 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,
1497 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);
1500 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,
1506 *cap = *adv7842_get_dv_timings_cap(sd);
1512 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1515 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),
1516 is_digital_input(sd) ? 250000 : 1000000,
1521 static int adv7842_query_dv_timings(struct v4l2_subdev *sd,
1524 struct adv7842_state *state = to_state(sd);
1528 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1537 if (read_stdi(sd, &stdi)) {
1539 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1547 if (is_digital_input(sd)) {
1552 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1553 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
1554 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000;
1555 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813);
1556 if (is_hdmi(sd)) {
1558 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8);
1561 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1562 hdmi_read(sd, 0x21);
1563 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1564 hdmi_read(sd, 0x23);
1565 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1566 hdmi_read(sd, 0x25);
1567 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1568 hdmi_read(sd, 0x2b)) / 2;
1569 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1570 hdmi_read(sd, 0x2f)) / 2;
1571 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1572 hdmi_read(sd, 0x33)) / 2;
1573 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1574 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1576 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1577 hdmi_read(sd, 0x0c);
1578 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1579 hdmi_read(sd, 0x2d)) / 2;
1580 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1581 hdmi_read(sd, 0x31)) / 2;
1582 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1583 hdmi_read(sd, 0x35)) / 2;
1589 adv7842_fill_optional_dv_timings_fields(sd, timings);
1603 if (!stdi2dv_timings(sd, &stdi, timings))
1606 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1607 if (!stdi2dv_timings(sd, &stdi, timings))
1610 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1611 if (stdi2dv_timings(sd, &stdi, timings)) {
1622 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1625 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1627 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1629 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1633 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1641 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:",
1646 static int adv7842_s_dv_timings(struct v4l2_subdev *sd,
1649 struct adv7842_state *state = to_state(sd);
1653 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
1659 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1665 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),
1669 adv7842_fill_optional_dv_timings_fields(sd, timings);
1673 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);
1676 err = configure_predefined_video_timings(sd, timings);
1680 configure_custom_video_timings(sd, bt);
1683 set_rgb_quantization_range(sd);
1687 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",
1692 static int adv7842_g_dv_timings(struct v4l2_subdev *sd,
1695 struct adv7842_state *state = to_state(sd);
1703 static void enable_input(struct v4l2_subdev *sd)
1705 struct adv7842_state *state = to_state(sd);
1707 set_rgb_quantization_range(sd);
1712 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
1715 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1716 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
1717 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
1720 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1726 static void disable_input(struct v4l2_subdev *sd)
1728 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */
1730 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
1731 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1734 static void sdp_csc_coeff(struct v4l2_subdev *sd,
1738 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);
1744 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);
1747 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);
1748 sdp_io_write(sd, 0xe1, c->A1);
1749 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);
1750 sdp_io_write(sd, 0xe3, c->A2);
1751 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);
1752 sdp_io_write(sd, 0xe5, c->A3);
1755 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);
1756 sdp_io_write(sd, 0xe7, c->A4);
1759 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);
1760 sdp_io_write(sd, 0xe9, c->B1);
1761 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);
1762 sdp_io_write(sd, 0xeb, c->B2);
1763 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);
1764 sdp_io_write(sd, 0xed, c->B3);
1767 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);
1768 sdp_io_write(sd, 0xef, c->B4);
1771 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);
1772 sdp_io_write(sd, 0xf1, c->C1);
1773 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);
1774 sdp_io_write(sd, 0xf3, c->C2);
1775 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);
1776 sdp_io_write(sd, 0xf5, c->C3);
1779 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);
1780 sdp_io_write(sd, 0xf7, c->C4);
1783 static void select_input(struct v4l2_subdev *sd,
1786 struct adv7842_state *state = to_state(sd);
1790 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */
1791 io_write(sd, 0x01, 0); /* prim mode */
1793 cp_write_and_or(sd, 0x81, 0xef, 0x10);
1795 afe_write(sd, 0x00, 0x00); /* power up ADC */
1796 afe_write(sd, 0xc8, 0x00); /* phase control */
1798 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */
1802 afe_write_and_or(sd, 0x02, 0x7f, 0x80);
1804 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1805 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/
1807 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/
1808 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/
1810 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */
1811 afe_write(sd, 0x12, 0x63); /* ADI recommend write */
1813 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */
1814 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */
1817 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */
1818 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */
1820 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */
1821 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */
1822 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */
1823 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */
1824 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */
1825 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */
1826 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */
1829 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);
1836 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1838 io_write(sd, 0x00, vid_std_select); /* video std */
1839 io_write(sd, 0x01, 0x02); /* prim mode */
1840 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs
1843 afe_write(sd, 0x00, 0x00); /* power up ADC */
1844 afe_write(sd, 0xc8, 0x00); /* phase control */
1847 io_write_and_or(sd, 0x02, 0x0f, 0x60);
1850 io_write_and_or(sd, 0x02, 0x0f, 0x10);
1856 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */
1857 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */
1860 cp_write(sd, 0x73, 0x10);
1861 cp_write(sd, 0x74, 0x04);
1862 cp_write(sd, 0x75, 0x01);
1863 cp_write(sd, 0x76, 0x00);
1865 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1866 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1867 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
1872 afe_write_and_or(sd, 0x02, 0x7f, 0x00);
1875 hdmi_write(sd, 0x00, 0x02); /* select port A */
1877 hdmi_write(sd, 0x00, 0x03); /* select port B */
1878 io_write(sd, 0x00, vid_std_select); /* video std */
1879 io_write(sd, 0x01, 5); /* prim mode */
1880 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs
1886 hdmi_write(sd, 0xc0, 0x00);
1887 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1888 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1889 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1890 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1891 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1892 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1893 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1894 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1895 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1897 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1898 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1899 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1900 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1901 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1902 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1903 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1904 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1905 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1906 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
1908 afe_write(sd, 0x00, 0xff); /* power down ADC */
1909 afe_write(sd, 0xc8, 0x40); /* phase control */
1912 cp_write(sd, 0x73, 0x10);
1913 cp_write(sd, 0x74, 0x04);
1914 cp_write(sd, 0x75, 0x01);
1915 cp_write(sd, 0x76, 0x00);
1920 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1921 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1922 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1925 cp_write(sd, 0xc3, 0x33); /* Component mode */
1928 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
1932 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",
1938 static int adv7842_s_routing(struct v4l2_subdev *sd,
1941 struct adv7842_state *state = to_state(sd);
1943 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);
1976 disable_input(sd);
1977 select_input(sd, state->vid_std_select);
1978 enable_input(sd);
1980 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);
1985 static int adv7842_enum_mbus_code(struct v4l2_subdev *sd,
2049 struct v4l2_subdev *sd = &state->sd;
2051 io_write_clr_set(sd, 0x02, 0x02,
2053 io_write(sd, 0x03, state->format->op_format_sel |
2055 io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state));
2056 io_write_clr_set(sd, 0x05, 0x01,
2058 set_rgb_quantization_range(sd);
2061 static int adv7842_get_format(struct v4l2_subdev *sd,
2065 struct adv7842_state *state = to_state(sd);
2072 if (!(sdp_read(sd, 0x5a) & 0x01))
2090 fmt = v4l2_subdev_get_try_format(sd, sd_state, format->pad);
2099 static int adv7842_set_format(struct v4l2_subdev *sd,
2103 struct adv7842_state *state = to_state(sd);
2110 return adv7842_get_format(sd, sd_state, format);
2122 fmt = v4l2_subdev_get_try_format(sd, sd_state, format->pad);
2132 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)
2136 io_write(sd, 0x46, 0x9c);
2138 io_write(sd, 0x5a, 0x10);
2140 io_write(sd, 0x73, 0x03);
2142 io_write(sd, 0x78, 0x03);
2144 io_write(sd, 0xa0, 0x09);
2146 io_write(sd, 0x69, 0x08);
2148 io_write(sd, 0x46, 0x0);
2149 io_write(sd, 0x5a, 0x0);
2150 io_write(sd, 0x73, 0x0);
2151 io_write(sd, 0x78, 0x0);
2152 io_write(sd, 0xa0, 0x0);
2153 io_write(sd, 0x69, 0x0);
2158 static void adv7842_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
2160 struct adv7842_state *state = to_state(sd);
2162 if ((cec_read(sd, 0x11) & 0x01) == 0) {
2163 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
2168 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",
2179 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
2185 nack_cnt = cec_read(sd, 0x14) & 0xf;
2188 low_drive_cnt = cec_read(sd, 0x14) >> 4;
2196 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
2202 static void adv7842_cec_isr(struct v4l2_subdev *sd, bool *handled)
2207 cec_irq = io_read(sd, 0x93) & 0x0f;
2211 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);
2212 adv7842_cec_tx_raw_status(sd, cec_irq);
2214 struct adv7842_state *state = to_state(sd);
2217 msg.len = cec_read(sd, 0x25) & 0x1f;
2225 msg.msg[i] = cec_read(sd, i + 0x15);
2226 cec_write(sd, 0x26, 0x01); /* re-enable rx */
2231 io_write(sd, 0x94, cec_irq);
2240 struct v4l2_subdev *sd = &state->sd;
2243 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */
2244 cec_write(sd, 0x2c, 0x01); /* cec soft reset */
2245 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */
2251 io_write_clr_set(sd, 0x96, 0x0f, 0x0f);
2252 cec_write(sd, 0x26, 0x01); /* enable rx */
2255 io_write_clr_set(sd, 0x96, 0x0f, 0x00);
2257 cec_write_clr_set(sd, 0x27, 0x70, 0x00);
2259 cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
2269 struct v4l2_subdev *sd = &state->sd;
2276 cec_write_clr_set(sd, 0x27, 0x70, 0);
2300 cec_write_clr_set(sd, 0x27, 0x10, 0x10);
2302 cec_write_clr_set(sd, 0x28, 0x0f, addr);
2306 cec_write_clr_set(sd, 0x27, 0x20, 0x20);
2308 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);
2312 cec_write_clr_set(sd, 0x27, 0x40, 0x40);
2314 cec_write_clr_set(sd, 0x29, 0x0f, addr);
2324 struct v4l2_subdev *sd = &state->sd;
2333 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);
2336 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
2342 cec_write(sd, i, msg->msg[i]);
2345 cec_write(sd, 0x10, len);
2347 cec_write(sd, 0x11, 0x01);
2358 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
2360 struct adv7842_state *state = to_state(sd);
2364 adv7842_irq_enable(sd, false);
2367 irq_status[0] = io_read(sd, 0x43);
2368 irq_status[1] = io_read(sd, 0x57);
2369 irq_status[2] = io_read(sd, 0x70);
2370 irq_status[3] = io_read(sd, 0x75);
2371 irq_status[4] = io_read(sd, 0x9d);
2372 irq_status[5] = io_read(sd, 0x66);
2376 io_write(sd, 0x44, irq_status[0]);
2378 io_write(sd, 0x58, irq_status[1]);
2380 io_write(sd, 0x71, irq_status[2]);
2382 io_write(sd, 0x76, irq_status[3]);
2384 io_write(sd, 0x9e, irq_status[4]);
2386 io_write(sd, 0x67, irq_status[5]);
2388 adv7842_irq_enable(sd, true);
2390 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__,
2404 if (is_digital_input(sd))
2411 v4l2_dbg(1, debug, sd,
2415 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);
2422 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2423 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI");
2424 set_rgb_quantization_range(sd);
2431 adv7842_cec_isr(sd, handled);
2436 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__);
2437 adv7842_s_detect_tx_5v_ctrl(sd);
2444 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2446 struct adv7842_state *state = to_state(sd);
2496 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e)
2498 struct adv7842_state *state = to_state(sd);
2529 err = edid_write_vga_segment(sd);
2540 adv7842_s_detect_tx_5v_ctrl(sd);
2542 err = edid_write_hdmi_segment(sd, e->pad);
2548 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);
2559 static void log_infoframe(struct v4l2_subdev *sd, const struct adv7842_cfg_read_infoframe *cri)
2565 struct i2c_client *client = v4l2_get_subdevdata(sd);
2568 if (!(io_read(sd, 0x60) & cri->present_mask)) {
2569 v4l2_info(sd, "%s infoframe not received\n", cri->desc);
2574 buffer[i] = infoframe_read(sd, cri->head_addr + i);
2579 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len);
2584 buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i);
2587 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc);
2594 static void adv7842_log_infoframes(struct v4l2_subdev *sd)
2604 if (!(hdmi_read(sd, 0x05) & 0x80)) {
2605 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2610 log_infoframe(sd, &cri[i]);
2635 static int adv7842_sdp_log_status(struct v4l2_subdev *sd)
2638 u8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;
2640 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");
2641 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",
2642 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);
2644 v4l2_info(sd, "SDP: free run: %s\n",
2645 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");
2646 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?
2663 v4l2_info(sd, "SDP: standard %s\n",
2664 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);
2665 v4l2_info(sd, "SDP: %s\n",
2666 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");
2667 v4l2_info(sd, "SDP: %s\n",
2668 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");
2669 v4l2_info(sd, "SDP: deinterlacer %s\n",
2670 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");
2671 v4l2_info(sd, "SDP: csc %s mode\n",
2672 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");
2677 static int adv7842_cp_log_status(struct v4l2_subdev *sd)
2680 struct adv7842_state *state = to_state(sd);
2682 u8 reg_io_0x02 = io_read(sd, 0x02);
2683 u8 reg_io_0x21 = io_read(sd, 0x21);
2684 u8 reg_rep_0x77 = rep_read(sd, 0x77);
2685 u8 reg_rep_0x7d = rep_read(sd, 0x7d);
2686 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2687 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2688 bool audio_mute = io_read(sd, 0x65) & 0x40;
2716 v4l2_info(sd, "-----Chip status-----\n");
2717 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2718 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",
2720 v4l2_info(sd, "EDID A %s, B %s\n",
2725 v4l2_info(sd, "HPD A %s, B %s\n",
2728 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
2737 v4l2_info(sd, "CEC Logical Address: 0x%x\n",
2742 v4l2_info(sd, "-----Signal status-----\n");
2744 v4l2_info(sd, "Cable detected (+5V power): %s\n",
2745 io_read(sd, 0x6f) & 0x02 ? "true" : "false");
2746 v4l2_info(sd, "TMDS signal detected: %s\n",
2747 (io_read(sd, 0x6a) & 0x02) ? "true" : "false");
2748 v4l2_info(sd, "TMDS signal locked: %s\n",
2749 (io_read(sd, 0x6a) & 0x20) ? "true" : "false");
2751 v4l2_info(sd, "Cable detected (+5V power):%s\n",
2752 io_read(sd, 0x6f) & 0x01 ? "true" : "false");
2753 v4l2_info(sd, "TMDS signal detected: %s\n",
2754 (io_read(sd, 0x6a) & 0x01) ? "true" : "false");
2755 v4l2_info(sd, "TMDS signal locked: %s\n",
2756 (io_read(sd, 0x6a) & 0x10) ? "true" : "false");
2758 v4l2_info(sd, "CP free run: %s\n",
2759 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
2760 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2761 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2762 (io_read(sd, 0x01) & 0x70) >> 4);
2764 v4l2_info(sd, "-----Video Timings-----\n");
2765 if (no_cp_signal(sd)) {
2766 v4l2_info(sd, "STDI: not locked\n");
2768 u32 bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
2769 u32 lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
2770 u32 lcvs = cp_read(sd, 0xb3) >> 3;
2771 u32 fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);
2772 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
2773 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
2774 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
2775 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
2776 v4l2_info(sd,
2779 (cp_read(sd, 0xb1) & 0x40) ?
2783 if (adv7842_query_dv_timings(sd, &timings))
2784 v4l2_info(sd, "No video detected\n");
2786 v4l2_print_dv_timings(sd->name, "Detected format: ",
2788 v4l2_print_dv_timings(sd->name, "Configured format: ",
2791 if (no_cp_signal(sd))
2794 v4l2_info(sd, "-----Color space-----\n");
2795 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2797 v4l2_info(sd, "Input color space: %s\n",
2799 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",
2804 v4l2_info(sd, "Color space conversion: %s\n",
2805 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);
2807 if (!is_digital_input(sd))
2810 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2811 v4l2_info(sd, "HDCP encrypted content: %s\n",
2812 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2813 v4l2_info(sd, "HDCP keys read: %s%s\n",
2814 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2815 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2816 if (!is_hdmi(sd))
2819 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2824 v4l2_info(sd, "Audio format: %s\n",
2825 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");
2827 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2828 (hdmi_read(sd, 0x5c) << 8) +
2829 (hdmi_read(sd, 0x5d) & 0xf0));
2830 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2831 (hdmi_read(sd, 0x5e) << 8) +
2832 hdmi_read(sd, 0x5f));
2833 v4l2_info(sd, "AV Mute: %s\n",
2834 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2835 v4l2_info(sd, "Deep color mode: %s\n",
2836 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);
2838 adv7842_log_infoframes(sd);
2843 static int adv7842_log_status(struct v4l2_subdev *sd)
2845 struct adv7842_state *state = to_state(sd);
2848 return adv7842_sdp_log_status(sd);
2849 return adv7842_cp_log_status(sd);
2852 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
2854 struct adv7842_state *state = to_state(sd);
2856 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2861 if (!(sdp_read(sd, 0x5A) & 0x01)) {
2863 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
2867 switch (sdp_read(sd, 0x52) & 0x0f) {
2907 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)
2910 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);
2911 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);
2912 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);
2913 sdp_io_write(sd, 0x97, s->hs_width & 0xff);
2914 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);
2915 sdp_io_write(sd, 0x99, s->de_beg & 0xff);
2916 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);
2917 sdp_io_write(sd, 0x9b, s->de_end & 0xff);
2918 sdp_io_write(sd, 0xa8, s->vs_beg_o);
2919 sdp_io_write(sd, 0xa9, s->vs_beg_e);
2920 sdp_io_write(sd, 0xaa, s->vs_end_o);
2921 sdp_io_write(sd, 0xab, s->vs_end_e);
2922 sdp_io_write(sd, 0xac, s->de_v_beg_o);
2923 sdp_io_write(sd, 0xad, s->de_v_beg_e);
2924 sdp_io_write(sd, 0xae, s->de_v_end_o);
2925 sdp_io_write(sd, 0xaf, s->de_v_end_e);
2928 sdp_io_write(sd, 0x94, 0x00);
2929 sdp_io_write(sd, 0x95, 0x00);
2930 sdp_io_write(sd, 0x96, 0x00);
2931 sdp_io_write(sd, 0x97, 0x20);
2932 sdp_io_write(sd, 0x98, 0x00);
2933 sdp_io_write(sd, 0x99, 0x00);
2934 sdp_io_write(sd, 0x9a, 0x00);
2935 sdp_io_write(sd, 0x9b, 0x00);
2936 sdp_io_write(sd, 0xa8, 0x04);
2937 sdp_io_write(sd, 0xa9, 0x04);
2938 sdp_io_write(sd, 0xaa, 0x04);
2939 sdp_io_write(sd, 0xab, 0x04);
2940 sdp_io_write(sd, 0xac, 0x04);
2941 sdp_io_write(sd, 0xad, 0x04);
2942 sdp_io_write(sd, 0xae, 0x04);
2943 sdp_io_write(sd, 0xaf, 0x04);
2947 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
2949 struct adv7842_state *state = to_state(sd);
2952 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2958 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);
2960 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);
2962 adv7842_s_sdp_io(sd, NULL);
2971 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
2973 struct adv7842_state *state = to_state(sd);
2975 v4l2_dbg(1, debug, sd, "%s:\n", __func__);
2986 static int adv7842_core_init(struct v4l2_subdev *sd)
2988 struct adv7842_state *state = to_state(sd);
2990 hdmi_write(sd, 0x48,
2994 disable_input(sd);
3000 rep_write_and_or(sd, 0x77, 0xd3, 0x20);
3003 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
3004 io_write(sd, 0x15, 0x80); /* Power up pads */
3007 io_write(sd, 0x02, 0xf0 | pdata->alt_gamma << 3);
3008 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
3014 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
3017 io_write_and_or(sd, 0x14, 0xc0,
3023 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable |
3027 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force |
3033 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */
3034 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */
3035 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
3036 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
3038 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
3039 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
3041 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);
3045 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */
3048 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */
3049 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */
3050 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
3051 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
3052 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
3054 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/
3055 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */
3056 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,
3058 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */
3059 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */
3060 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */
3061 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */
3068 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */
3071 select_input(sd, pdata->vid_std_select);
3073 enable_input(sd);
3077 hdmi_write(sd, 0x69, 0x5c);
3080 hdmi_write(sd, 0x69, 0xa3);
3082 io_write_and_or(sd, 0x20, 0xcf, 0x00);
3086 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);
3087 io_write(sd, 0x33, 0x40);
3090 io_write(sd, 0x40, 0xf2); /* Configure INT1 */
3092 adv7842_irq_enable(sd, true);
3094 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
3099 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)
3112 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */
3113 io_write(sd, 0x01, 0x00); /* Program SDP mode */
3114 afe_write(sd, 0x80, 0x92); /* SDP Recommended Write */
3115 afe_write(sd, 0x9B, 0x01); /* SDP Recommended Write ADV7844ES1 */
3116 afe_write(sd, 0x9C, 0x60); /* SDP Recommended Write ADV7844ES1 */
3117 afe_write(sd, 0x9E, 0x02); /* SDP Recommended Write ADV7844ES1 */
3118 afe_write(sd, 0xA0, 0x0B); /* SDP Recommended Write ADV7844ES1 */
3119 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */
3120 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */
3121 io_write(sd, 0x15, 0xBA); /* Enable outputs */
3122 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */
3123 io_write(sd, 0xFF, 0x04); /* Reset memory controller */
3127 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */
3128 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */
3129 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */
3130 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */
3131 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */
3132 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */
3133 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */
3134 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */
3135 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */
3136 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */
3137 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */
3141 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */
3142 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */
3147 u8 result = sdp_io_read(sd, 0xdb);
3158 v4l2_dbg(1, debug, sd,
3167 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,
3170 io_write(sd, 0xf1, pdata->i2c_sdp << 1);
3171 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);
3172 io_write(sd, 0xf3, pdata->i2c_avlink << 1);
3173 io_write(sd, 0xf4, pdata->i2c_cec << 1);
3174 io_write(sd, 0xf5, pdata->i2c_infoframe << 1);
3176 io_write(sd, 0xf8, pdata->i2c_afe << 1);
3177 io_write(sd, 0xf9, pdata->i2c_repeater << 1);
3178 io_write(sd, 0xfa, pdata->i2c_edid << 1);
3179 io_write(sd, 0xfb, pdata->i2c_hdmi << 1);
3181 io_write(sd, 0xfd, pdata->i2c_cp << 1);
3182 io_write(sd, 0xfe, pdata->i2c_vdp << 1);
3185 static int adv7842_command_ram_test(struct v4l2_subdev *sd)
3187 struct i2c_client *client = v4l2_get_subdevdata(sd);
3188 struct adv7842_state *state = to_state(sd);
3197 v4l2_info(sd, "no sdram or no ddr sdram\n");
3201 main_reset(sd);
3203 adv7842_rewrite_i2c_addresses(sd, pdata);
3206 ret = adv7842_ddr_ram_test(sd);
3208 main_reset(sd);
3210 adv7842_rewrite_i2c_addresses(sd, pdata);
3213 adv7842_core_init(sd);
3215 disable_input(sd);
3217 select_input(sd, state->vid_std_select);
3219 enable_input(sd);
3221 edid_write_vga_segment(sd);
3222 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A);
3223 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B);
3229 adv7842_s_dv_timings(sd, &timings);
3234 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
3238 return adv7842_command_ram_test(sd);
3243 static int adv7842_subscribe_event(struct v4l2_subdev *sd,
3249 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
3251 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
3257 static int adv7842_registered(struct v4l2_subdev *sd)
3259 struct adv7842_state *state = to_state(sd);
3260 struct i2c_client *client = v4l2_get_subdevdata(sd);
3269 static void adv7842_unregistered(struct v4l2_subdev *sd)
3271 struct adv7842_state *state = to_state(sd);
3360 static void adv7842_unregister_clients(struct v4l2_subdev *sd)
3362 struct adv7842_state *state = to_state(sd);
3388 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc,
3391 struct i2c_client *client = v4l2_get_subdevdata(sd);
3394 io_write(sd, io_reg, addr << 1);
3397 v4l2_err(sd, "no %s i2c addr configured\n", desc);
3401 cp = i2c_new_dummy_device(client->adapter, io_read(sd, io_reg) >> 1);
3403 v4l2_err(sd, "register %s on i2c addr 0x%x failed with %ld\n",
3411 static int adv7842_register_clients(struct v4l2_subdev *sd)
3413 struct adv7842_state *state = to_state(sd);
3416 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3);
3417 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4);
3418 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5);
3419 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2);
3420 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1);
3421 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8);
3422 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9);
3423 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa);
3424 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb);
3425 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd);
3426 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe);
3452 struct v4l2_subdev *sd;
3478 sd = &state->sd;
3479 v4l2_i2c_subdev_init(sd, client, &adv7842_ops);
3480 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
3481 sd->internal_ops = &adv7842_int_ops;
3491 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);
3496 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",
3502 main_reset(sd);
3536 sd->ctrl_handler = hdl;
3541 if (adv7842_s_detect_tx_5v_ctrl(sd)) {
3546 if (adv7842_register_clients(sd) < 0) {
3548 v4l2_err(sd, "failed to create all i2c clients\n");
3556 sd->entity.function = MEDIA_ENT_F_DV_DECODER;
3560 err = media_entity_pads_init(&sd->entity, ADV7842_PAD_SOURCE + 1,
3565 err = adv7842_core_init(sd);
3578 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3583 media_entity_cleanup(&sd->entity);
3587 adv7842_unregister_clients(sd);
3597 struct v4l2_subdev *sd = i2c_get_clientdata(client);
3598 struct adv7842_state *state = to_state(sd);
3600 adv7842_irq_enable(sd, false);
3602 v4l2_device_unregister_subdev(sd);
3603 media_entity_cleanup(&sd->entity);
3604 adv7842_unregister_clients(sd);
3605 v4l2_ctrl_handler_free(sd->ctrl_handler);