Lines Matching refs:hdmi_write
509 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
518 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
938 hdmi_write(sd, reg->reg & 0xff, val);
1715 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1731 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1875 hdmi_write(sd, 0x00, 0x02); /* select port A */
1877 hdmi_write(sd, 0x00, 0x03); /* select port B */
1886 hdmi_write(sd, 0xc0, 0x00);
1887 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */
1888 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */
1889 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */
1890 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */
1891 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1892 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1893 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */
1894 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */
1895 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,
1897 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */
1898 hdmi_write(sd, 0x85, 0x1f); /* equaliser */
1899 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */
1900 hdmi_write(sd, 0x89, 0x04); /* equaliser */
1901 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */
1902 hdmi_write(sd, 0x93, 0x04); /* equaliser */
1903 hdmi_write(sd, 0x94, 0x1e); /* equaliser */
1904 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */
1905 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */
1906 hdmi_write(sd, 0x9d, 0x02); /* equaliser */
2990 hdmi_write(sd, 0x48,
3077 hdmi_write(sd, 0x69, 0x5c);
3080 hdmi_write(sd, 0x69, 0xa3);