Lines Matching defs:adv7180_write
242 static int adv7180_write(struct adv7180_state *state, unsigned int reg,
517 ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val);
574 adv7180_write(state, ADV7180_REG_ANALOG_CLAMP_CTL, reg);
579 adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg);
585 adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg);
602 ret = adv7180_write(state, ADV7180_REG_BRI, val);
606 ret = adv7180_write(state, ADV7180_REG_HUE, -val);
609 ret = adv7180_write(state, ADV7180_REG_CON, val);
616 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val);
619 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);
624 adv7180_write(state, 0x80d9, 0x44);
625 adv7180_write(state, ADV7180_REG_FLCONTROL,
629 adv7180_write(state, 0x80d9, 0xc4);
630 adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);
957 adv7180_write(state, ADV7180_REG_ICR3, isr3);
977 ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
983 return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END,
989 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,
1003 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret);
1009 adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,
1013 adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,
1018 adv7180_write(state, 0x0080, 0x51);
1019 adv7180_write(state, 0x0081, 0x51);
1020 adv7180_write(state, 0x0082, 0x68);
1025 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e);
1026 adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57);
1027 adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0);
1032 adv7180_write(state,
1036 adv7180_write(state,
1040 adv7180_write(state,
1044 adv7180_write(state,
1050 adv7180_write(state,
1053 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c);
1054 adv7180_write(state, ADV7180_REG_CTRL_2, 0x40);
1057 adv7180_write(state, 0x0013, 0x00);
1065 return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL,
1128 ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);
1133 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00);
1134 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff);
1142 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41);
1145 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01);
1155 adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]);
1159 adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8);
1160 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90);
1161 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0);
1162 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08);
1163 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0);
1165 adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0);
1166 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0);
1167 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10);
1168 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c);
1169 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00);
1349 adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);
1365 ret = adv7180_write(state, ADV7180_REG_ICONF1,
1371 ret = adv7180_write(state, ADV7180_REG_IMR1, 0);
1375 ret = adv7180_write(state, ADV7180_REG_IMR2, 0);
1380 ret = adv7180_write(state, ADV7180_REG_IMR3,
1385 ret = adv7180_write(state, ADV7180_REG_IMR4, 0);