Lines Matching refs:reg
683 static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
688 u8 b0[] = { reg >> 8, reg & 0xff };
701 reg, ret);
707 reg, buf);
712 static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
721 "%s: i2c wr reg=%04x: len=%d is too big!\n",
722 KBUILD_MODNAME, reg, count);
726 buf[0] = reg >> 8;
727 buf[1] = reg & 0xff;
731 __func__, reg, count, data);
737 reg, data[0], count, ret);
744 static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
748 return stv090x_write_regs(state, reg, &tmp, 1);
753 u32 reg;
771 reg = STV090x_READ_DEMOD(state, I2CRPT);
774 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1);
775 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
780 STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 0);
781 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
1199 u32 reg;
1204 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1205 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, enable);
1206 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1213 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1214 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, enable);
1215 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1267 u32 reg;
1272 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1273 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1274 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1275 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1297 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1298 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1299 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1300 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1302 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1303 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1304 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1345 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1346 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
1347 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
1348 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1350 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
1351 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
1352 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1399 u32 reg, freq_abs;
1403 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1404 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f);
1405 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1509 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1510 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1511 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1512 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1514 reg = STV090x_READ_DEMOD(state, DMDCFG2);
1515 STV090x_SETFIELD_Px(reg, S1S2_SEQUENTIAL_FIELD, 0x0);
1516 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
1587 u32 agc2_min = 0xffff, agc2 = 0, freq_init, freq_step, reg;
1592 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1593 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0);
1594 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1595 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1684 u32 srate_coarse = 0, agc2 = 0, car_step = 1200, reg;
1692 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1693 STV090x_SETFIELD_Px(reg, I2C_DEMOD_MODE_FIELD, 0x1f); /* Demod RESET */
1694 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1704 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1705 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 1);
1706 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0);
1707 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1774 reg = STV090x_READ_DEMOD(state, DSTATUS);
1775 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
1816 if (state->config->tuner_get_status(fe, ®) < 0)
1820 if (reg)
1846 u32 srate_coarse, freq_coarse, sym, reg;
1866 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1867 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
1868 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1945 u32 reg;
1949 reg = STV090x_READ_DEMOD(state, DMDSTATE);
1950 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
1961 reg = STV090x_READ_DEMOD(state, DSTATUS);
1962 lock = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
1978 u32 agc2, reg, srate_coarse;
2037 reg = STV090x_READ_DEMOD(state, DSTATUS2);
2038 if ((STV090x_GETFIELD_Px(reg, CFR_OVERFLOW_FIELD) == 0x01) &&
2039 (STV090x_GETFIELD_Px(reg, DEMOD_DELOCK_FIELD) == 0x01))
2061 u32 reg;
2074 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2075 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00); /* stop carrier offset search */
2076 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2098 reg = STV090x_READ_DEMOD(state, DSTATUS);
2099 if (STV090x_GETFIELD_Px(reg, TMGLOCK_QUALITY_FIELD) >= 2)
2131 u32 reg;
2206 if (state->config->tuner_get_status(fe, ®) < 0)
2208 if (reg)
2336 u32 reg;
2360 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2361 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x1); /* stop DVB-S2 packet delin */
2362 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2385 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2386 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0);
2387 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2399 u32 reg;
2464 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2465 if ((lock) && (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == STV090x_DVBS2)) {
2468 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2469 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2472 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2473 dvbs2_fly_wheel = STV090x_GETFIELD_Px(reg, FLYWHEEL_CPT_FIELD);
2500 u32 reg;
2503 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2504 if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 2)
2506 else if (STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD) == 3) {
2507 reg = STV090x_READ_DEMOD(state, FECM);
2508 if (STV090x_GETFIELD_Px(reg, DSS_DVB_FIELD) == 1)
2545 u32 reg, rate;
2547 reg = STV090x_READ_DEMOD(state, VITCURPUN);
2548 rate = STV090x_GETFIELD_Px(reg, VIT_CURPUN_FIELD);
2588 u32 reg;
2621 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2622 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2623 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2624 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
2625 reg = STV090x_READ_DEMOD(state, TMGOBS);
2626 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2627 reg = STV090x_READ_DEMOD(state, FECM);
2628 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
2841 u32 reg;
2850 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2851 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2852 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 0);
2853 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2856 reg = STV090x_READ_DEMOD(state, DEMOD);
2857 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
2858 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x01);
2859 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2884 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2885 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 0);
2886 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2887 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2896 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2897 modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2898 pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2950 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2951 STV090x_SETFIELD_Px(reg, DVBS1_ENABLE_FIELD, 1);
2952 STV090x_SETFIELD_Px(reg, DVBS2_ENABLE_FIELD, 1);
2953 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2960 reg = STV090x_READ_DEMOD(state, TMGOBS);
2964 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2965 STV090x_SETFIELD_Px(reg, SCAN_ENABLE_FIELD, 0x00);
2966 STV090x_SETFIELD_Px(reg, CFR_AUTOSCAN_FIELD, 0x00);
2967 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
3083 u32 reg;
3086 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3087 stat = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3097 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3098 lock = STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD);
3102 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3103 lock = STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD);
3116 u32 reg;
3128 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3129 lock = STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD);
3140 u32 reg;
3144 reg = STV090x_READ_DEMOD(state, DEMOD);
3145 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 0x00);
3146 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3150 reg = STV090x_READ_DEMOD(state, DEMOD);
3151 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 0x00);
3152 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3166 u32 reg;
3170 reg = STV090x_READ_DEMOD(state, TSCFGH);
3171 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* Stop path 1 stream merger */
3172 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3254 reg = state->config->tuner_bbgain;
3255 if (reg == 0)
3256 reg = 10; /* default: 10dB */
3257 if (state->config->tuner_set_bbgain(fe, reg) < 0)
3279 if (state->config->tuner_get_status(fe, ®) < 0)
3284 if (reg)
3312 reg = STV090x_READ_DEMOD(state, DEMOD);
3313 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
3317 STV090x_SETFIELD_Px(reg, MANUAL_SXROLLOFF_FIELD, 1);
3320 STV090x_SETFIELD_Px(reg, MANUAL_S2ROLLOFF_FIELD, 1);
3322 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3363 reg = STV090x_READ_DEMOD(state, TSCFGH);
3364 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3365 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3370 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 1); /* merger reset */
3371 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3374 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0); /* release merger reset */
3375 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3385 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3386 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 1);
3387 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
3390 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3391 STV090x_SETFIELD_Px(reg, RESET_UPKO_COUNT, 0);
3392 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
3438 u32 reg;
3442 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3443 STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x00);
3444 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3448 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3449 STV090x_SETFIELD_Px(reg, FILTER_EN_FIELD, 0x01);
3450 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3515 u32 reg, dstatus;
3524 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3525 search_state = STV090x_GETFIELD_Px(reg, HEADER_MODE_FIELD);
3537 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3538 if (STV090x_GETFIELD_Px(reg, PKTDELIN_LOCK_FIELD)) {
3540 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3541 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD))
3550 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3551 if (STV090x_GETFIELD_Px(reg, LOCKEDVIT_FIELD)) {
3553 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3554 if (STV090x_GETFIELD_Px(reg, TSFIFO_LINEOK_FIELD))
3569 u32 reg, h, m, l;
3577 reg = STV090x_READ_DEMOD(state, ERRCNT22);
3578 h = STV090x_GETFIELD_Px(reg, ERR_CNT2_FIELD);
3580 reg = STV090x_READ_DEMOD(state, ERRCNT21);
3581 m = STV090x_GETFIELD_Px(reg, ERR_CNT21_FIELD);
3583 reg = STV090x_READ_DEMOD(state, ERRCNT20);
3584 l = STV090x_GETFIELD_Px(reg, ERR_CNT20_FIELD);
3654 u32 reg;
3658 reg = STV090x_READ_DEMOD(state, AGCIQIN1);
3659 agc_1 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3660 reg = STV090x_READ_DEMOD(state, AGCIQIN0);
3661 agc_0 = STV090x_GETFIELD_Px(reg, AGCIQ_VALUE_FIELD);
3678 u32 reg_0, reg_1, reg, i;
3686 reg = STV090x_READ_DEMOD(state, DSTATUS);
3687 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3711 reg = STV090x_READ_DEMOD(state, DSTATUS);
3712 lock_f = STV090x_GETFIELD_Px(reg, LOCK_DEFINITIF_FIELD);
3741 u32 reg;
3743 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3746 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3747 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3748 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3750 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3751 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3756 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, 0);
3757 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3758 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3780 u32 reg, idle = 0, fifo_full = 1;
3783 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3785 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD,
3787 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3788 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3790 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3791 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3794 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3795 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3801 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3802 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3808 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3809 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3810 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3816 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3817 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3832 u32 reg, idle = 0, fifo_full = 1;
3836 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3846 STV090x_SETFIELD_Px(reg, DISTX_MODE_FIELD, mode);
3847 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 1);
3848 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3850 STV090x_SETFIELD_Px(reg, DISEQC_RESET_FIELD, 0);
3851 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3854 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 1);
3855 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3859 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3860 fifo_full = STV090x_GETFIELD_Px(reg, FIFO_FULL_FIELD);
3866 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3867 STV090x_SETFIELD_Px(reg, DIS_PRECHARGE_FIELD, 0);
3868 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3874 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3875 idle = STV090x_GETFIELD_Px(reg, TX_IDLE_FIELD);
3889 u32 reg = 0, i = 0, rx_end = 0;
3894 reg = STV090x_READ_DEMOD(state, DISRX_ST0);
3895 rx_end = STV090x_GETFIELD_Px(reg, RX_END_FIELD);
3899 reply->msg_len = STV090x_GETFIELD_Px(reg, FIFO_BYTENBR_FIELD);
3910 u32 reg;
3933 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3934 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 0);
3935 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3938 reg = stv090x_read_reg(state, STV090x_TSTTNR2);
3939 STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 0);
3940 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
3945 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
3946 if (STV090x_GETFIELD(reg, ADC2_PON_FIELD) == 0)
3950 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
3952 STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 1);
3954 STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 1);
3958 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1);
3959 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
3961 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
3963 STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 1);
3965 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 1);
3969 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1);
3970 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
3976 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
3977 STV090x_SETFIELD(reg, ADC2_PON_FIELD, 0);
3978 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
3981 reg = stv090x_read_reg(state, STV090x_TSTTNR4);
3982 STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 0);
3983 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
3988 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3989 if (STV090x_GETFIELD(reg, ADC1_PON_FIELD) == 0)
3993 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
3995 STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 1);
3997 STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 1);
4001 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 1);
4002 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4004 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
4006 STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 1);
4008 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 1);
4012 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 1);
4013 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4024 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4025 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x01);
4026 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
4046 u32 reg;
4055 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4056 STV090x_SETFIELD(reg, STANDBY_FIELD, 0x00);
4057 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
4063 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
4064 STV090x_SETFIELD(reg, ADC1_PON_FIELD, 1);
4065 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
4068 reg = stv090x_read_reg(state, STV090x_TSTTNR2);
4069 STV090x_SETFIELD(reg, DISEQC1_PON_FIELD, 1);
4070 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
4074 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
4076 STV090x_SETFIELD(reg, STOP_CLKPKDT1_FIELD, 0);
4078 STV090x_SETFIELD(reg, STOP_CLKADCI1_FIELD, 0);
4080 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0);
4081 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4083 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
4085 STV090x_SETFIELD(reg, STOP_CLKSAMP1_FIELD, 0);
4087 STV090x_SETFIELD(reg, STOP_CLKVIT1_FIELD, 0);
4089 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0);
4090 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4096 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
4097 STV090x_SETFIELD(reg, ADC2_PON_FIELD, 1);
4098 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
4101 reg = stv090x_read_reg(state, STV090x_TSTTNR4);
4102 STV090x_SETFIELD(reg, DISEQC2_PON_FIELD, 1);
4103 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
4107 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
4109 STV090x_SETFIELD(reg, STOP_CLKPKDT2_FIELD, 0);
4111 STV090x_SETFIELD(reg, STOP_CLKADCI2_FIELD, 0);
4113 STV090x_SETFIELD(reg, STOP_CLKFEC_FIELD, 0);
4114 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4116 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
4118 STV090x_SETFIELD(reg, STOP_CLKSAMP2_FIELD, 0);
4120 STV090x_SETFIELD(reg, STOP_CLKVIT2_FIELD, 0);
4122 STV090x_SETFIELD(reg, STOP_CLKTS_FIELD, 0);
4123 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4158 u32 reg = 0;
4160 reg = stv090x_read_reg(state, STV090x_GENCFG);
4165 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
4172 reg = stv090x_read_reg(state, STV090x_TSTRES0);
4173 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
4174 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4176 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
4177 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4231 reg = stv090x_read_reg(state, STV090x_TSTRES0);
4232 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x1);
4233 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4235 STV090x_SETFIELD(reg, FRESFEC_FIELD, 0x0);
4236 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4239 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
4240 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x01);
4241 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
4243 STV090x_SETFIELD_Px(reg, ALGOSWRST_FIELD, 0x00);
4244 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
4259 u32 div, reg;
4263 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4264 ratio = STV090x_GETFIELD(reg, SELX1RATIO_FIELD) ? 4 : 6;
4272 u32 reg, div, clk_sel;
4274 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4275 clk_sel = ((STV090x_GETFIELD(reg, SELX1RATIO_FIELD) == 1) ? 4 : 6);
4279 reg = stv090x_read_reg(state, STV090x_NCOARSE);
4280 STV090x_SETFIELD(reg, M_DIV_FIELD, div);
4281 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
4301 u32 reg;
4318 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4319 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4320 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4322 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
4323 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4324 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4367 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4368 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4369 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4371 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4372 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 0);
4373 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4404 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4405 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4406 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4407 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4408 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4413 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4414 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4415 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4416 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4417 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4422 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4423 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4424 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4425 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4426 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4431 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4432 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4433 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4434 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4435 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4445 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4446 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4447 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4448 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4449 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4454 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4455 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4456 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4457 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4458 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4463 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4464 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4465 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4466 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4467 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4472 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4473 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4474 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4475 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4476 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4508 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4509 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4510 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4540 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
4541 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4542 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4548 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4549 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4550 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4552 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4553 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4556 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4557 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4558 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4560 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4561 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4572 u32 reg;
4604 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4605 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4606 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4607 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4612 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4613 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x00);
4614 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4615 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4620 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4621 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4622 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x00);
4623 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4628 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4629 STV090x_SETFIELD_Px(reg, TSFIFO_SERIAL_FIELD, 0x01);
4630 STV090x_SETFIELD_Px(reg, TSFIFO_DVBCI_FIELD, 0x01);
4631 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4663 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4664 STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3);
4665 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4671 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4672 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x01);
4673 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4675 STV090x_SETFIELD_Px(reg, RST_HWARE_FIELD, 0x00);
4676 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4689 u32 reg;
4722 reg = STV090x_READ_DEMOD(state, TNRCFG2);
4723 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
4724 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
4726 reg = STV090x_READ_DEMOD(state, DEMOD);
4727 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
4728 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
4771 u32 reg = 0;
4808 STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level);
4809 if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0)
4812 if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0)
4855 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
4856 STV090x_SETFIELD(reg, ADC1_INMODE_FIELD,
4858 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
4862 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
4863 STV090x_SETFIELD(reg, ADC2_INMODE_FIELD,
4865 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
4883 u8 reg = 0;
4885 STV090x_SETFIELD(reg, GPIOx_OPD_FIELD, dir);
4886 STV090x_SETFIELD(reg, GPIOx_CONFIG_FIELD, value);
4887 STV090x_SETFIELD(reg, GPIOx_XOR_FIELD, xor_value);
4889 return stv090x_write_reg(state, STV090x_GPIOxCFG(gpio), reg);