Lines Matching defs:state
683 static int stv090x_read_reg(struct stv090x_state *state, unsigned int reg)
685 const struct stv090x_config *config = state->config;
696 ret = i2c_transfer(state->i2c, msg, 2);
705 if (unlikely(*state->verbose >= FE_DEBUGREG))
712 static int stv090x_write_regs(struct stv090x_state *state, unsigned int reg, u8 *data, u32 count)
714 const struct stv090x_config *config = state->config;
733 ret = i2c_transfer(state->i2c, &i2c_msg, 1);
744 static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 data)
748 return stv090x_write_regs(state, reg, &tmp, 1);
751 static int stv090x_i2c_gate_ctrl(struct stv090x_state *state, int enable)
756 * NOTE! A lock is used as a FSM to control the state in which
765 if (state->config->tuner_i2c_lock)
766 state->config->tuner_i2c_lock(&state->frontend, 1);
768 mutex_lock(&state->internal->tuner_lock);
771 reg = STV090x_READ_DEMOD(state, I2CRPT);
775 if (STV090x_WRITE_DEMOD(state, I2CRPT, reg) < 0)
781 if ((STV090x_WRITE_DEMOD(state, I2CRPT, reg)) < 0)
786 if (state->config->tuner_i2c_lock)
787 state->config->tuner_i2c_lock(&state->frontend, 0);
789 mutex_unlock(&state->internal->tuner_lock);
795 if (state->config->tuner_i2c_lock)
796 state->config->tuner_i2c_lock(&state->frontend, 0);
798 mutex_unlock(&state->internal->tuner_lock);
802 static void stv090x_get_lock_tmg(struct stv090x_state *state)
804 switch (state->algo) {
807 if (state->srate <= 1500000) { /*10Msps< SR <=15Msps*/
808 state->DemodTimeout = 1500;
809 state->FecTimeout = 400;
810 } else if (state->srate <= 5000000) { /*10Msps< SR <=15Msps*/
811 state->DemodTimeout = 1000;
812 state->FecTimeout = 300;
814 state->DemodTimeout = 700;
815 state->FecTimeout = 100;
823 if (state->srate <= 1000000) { /*SR <=1Msps*/
824 state->DemodTimeout = 4500;
825 state->FecTimeout = 1700;
826 } else if (state->srate <= 2000000) { /*1Msps < SR <= 2Msps */
827 state->DemodTimeout = 2500;
828 state->FecTimeout = 1100;
829 } else if (state->srate <= 5000000) { /*2Msps < SR <= 5Msps */
830 state->DemodTimeout = 1000;
831 state->FecTimeout = 550;
832 } else if (state->srate <= 10000000) { /*5Msps < SR <= 10Msps */
833 state->DemodTimeout = 700;
834 state->FecTimeout = 250;
835 } else if (state->srate <= 20000000) { /*10Msps < SR <= 20Msps */
836 state->DemodTimeout = 400;
837 state->FecTimeout = 130;
839 state->DemodTimeout = 300;
840 state->FecTimeout = 100;
845 if (state->algo == STV090x_WARM_SEARCH)
846 state->DemodTimeout /= 2;
849 static int stv090x_set_srate(struct stv090x_state *state, u32 srate)
855 sym /= (state->internal->mclk >> 12);
858 sym /= (state->internal->mclk >> 10);
861 sym /= (state->internal->mclk >> 7);
864 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0x7f) < 0) /* MSB */
866 if (STV090x_WRITE_DEMOD(state, SFRINIT0, (sym & 0xff)) < 0) /* LSB */
875 static int stv090x_set_max_srate(struct stv090x_state *state, u32 clk, u32 srate)
882 sym /= (state->internal->mclk >> 12);
885 sym /= (state->internal->mclk >> 10);
888 sym /= (state->internal->mclk >> 7);
892 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0) /* MSB */
894 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0) /* LSB */
897 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x7f) < 0) /* MSB */
899 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xff) < 0) /* LSB */
909 static int stv090x_set_min_srate(struct stv090x_state *state, u32 clk, u32 srate)
916 sym /= (state->internal->mclk >> 12);
919 sym /= (state->internal->mclk >> 10);
922 sym /= (state->internal->mclk >> 7);
925 if (STV090x_WRITE_DEMOD(state, SFRLOW1, ((sym >> 8) & 0x7f)) < 0) /* MSB */
927 if (STV090x_WRITE_DEMOD(state, SFRLOW0, (sym & 0xff)) < 0) /* LSB */
955 static int stv090x_set_vit_thacq(struct stv090x_state *state)
957 if (STV090x_WRITE_DEMOD(state, VTH12, 0x96) < 0)
959 if (STV090x_WRITE_DEMOD(state, VTH23, 0x64) < 0)
961 if (STV090x_WRITE_DEMOD(state, VTH34, 0x36) < 0)
963 if (STV090x_WRITE_DEMOD(state, VTH56, 0x23) < 0)
965 if (STV090x_WRITE_DEMOD(state, VTH67, 0x1e) < 0)
967 if (STV090x_WRITE_DEMOD(state, VTH78, 0x19) < 0)
975 static int stv090x_set_vit_thtracq(struct stv090x_state *state)
977 if (STV090x_WRITE_DEMOD(state, VTH12, 0xd0) < 0)
979 if (STV090x_WRITE_DEMOD(state, VTH23, 0x7d) < 0)
981 if (STV090x_WRITE_DEMOD(state, VTH34, 0x53) < 0)
983 if (STV090x_WRITE_DEMOD(state, VTH56, 0x2f) < 0)
985 if (STV090x_WRITE_DEMOD(state, VTH67, 0x24) < 0)
987 if (STV090x_WRITE_DEMOD(state, VTH78, 0x1f) < 0)
995 static int stv090x_set_viterbi(struct stv090x_state *state)
997 switch (state->search_mode) {
999 if (STV090x_WRITE_DEMOD(state, FECM, 0x10) < 0) /* DVB-S and DVB-S2 */
1001 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x3f) < 0) /* all puncture rate */
1005 if (STV090x_WRITE_DEMOD(state, FECM, 0x00) < 0) /* disable DSS */
1007 switch (state->fec) {
1009 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
1014 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
1019 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x04) < 0)
1024 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x08) < 0)
1029 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x20) < 0)
1034 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x2f) < 0) /* all */
1040 if (STV090x_WRITE_DEMOD(state, FECM, 0x80) < 0)
1042 switch (state->fec) {
1044 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x01) < 0)
1049 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x02) < 0)
1054 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x10) < 0)
1059 if (STV090x_WRITE_DEMOD(state, PRVIT, 0x13) < 0) /* 1/2, 2/3, 6/7 */
1073 static int stv090x_stop_modcod(struct stv090x_state *state)
1075 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1077 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
1079 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
1081 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
1083 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
1085 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
1087 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
1089 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xff) < 0)
1091 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xff) < 0)
1093 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xff) < 0)
1095 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xff) < 0)
1097 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xff) < 0)
1099 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xff) < 0)
1101 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xff) < 0)
1103 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
1105 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xff) < 0)
1113 static int stv090x_activate_modcod(struct stv090x_state *state)
1115 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1117 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xfc) < 0)
1119 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xcc) < 0)
1121 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xcc) < 0)
1123 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xcc) < 0)
1125 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xcc) < 0)
1127 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xcc) < 0)
1129 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
1131 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
1133 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
1135 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
1137 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
1139 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
1141 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
1143 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xcc) < 0)
1145 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
1154 static int stv090x_activate_modcod_single(struct stv090x_state *state)
1157 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
1159 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xf0) < 0)
1161 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0x00) < 0)
1163 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0x00) < 0)
1165 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0x00) < 0)
1167 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0x00) < 0)
1169 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0x00) < 0)
1171 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0x00) < 0)
1173 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0x00) < 0)
1175 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0x00) < 0)
1177 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0x00) < 0)
1179 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0x00) < 0)
1181 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0x00) < 0)
1183 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0x00) < 0)
1185 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0x00) < 0)
1187 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0x0f) < 0)
1197 static int stv090x_vitclk_ctl(struct stv090x_state *state, int enable)
1201 switch (state->demod) {
1203 mutex_lock(&state->internal->demod_lock);
1204 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1206 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1208 mutex_unlock(&state->internal->demod_lock);
1212 mutex_lock(&state->internal->demod_lock);
1213 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
1215 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
1217 mutex_unlock(&state->internal->demod_lock);
1226 mutex_unlock(&state->internal->demod_lock);
1231 static int stv090x_dvbs_track_crl(struct stv090x_state *state)
1233 if (state->internal->dev_ver >= 0x30) {
1235 if (state->srate >= 15000000) {
1236 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2b) < 0)
1238 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1a) < 0)
1240 } else if ((state->srate >= 7000000) && (15000000 > state->srate)) {
1241 if (STV090x_WRITE_DEMOD(state, ACLC, 0x0c) < 0)
1243 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1b) < 0)
1245 } else if (state->srate < 7000000) {
1246 if (STV090x_WRITE_DEMOD(state, ACLC, 0x2c) < 0)
1248 if (STV090x_WRITE_DEMOD(state, BCLC, 0x1c) < 0)
1254 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0)
1256 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1265 static int stv090x_delivery_search(struct stv090x_state *state)
1269 switch (state->search_mode) {
1272 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1275 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1281 if (stv090x_vitclk_ctl(state, 0) < 0)
1284 if (stv090x_dvbs_track_crl(state) < 0)
1287 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x22) < 0) /* disable DVB-S2 */
1290 if (stv090x_set_vit_thacq(state) < 0)
1292 if (stv090x_set_viterbi(state) < 0)
1297 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1300 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1304 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1307 if (stv090x_vitclk_ctl(state, 1) < 0)
1310 if (STV090x_WRITE_DEMOD(state, ACLC, 0x1a) < 0) /* stop DVB-S CR loop */
1312 if (STV090x_WRITE_DEMOD(state, BCLC, 0x09) < 0)
1315 if (state->internal->dev_ver <= 0x20) {
1317 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1321 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1325 if (state->demod_mode != STV090x_SINGLE) {
1327 if (stv090x_activate_modcod(state) < 0)
1334 if (stv090x_activate_modcod_single(state) < 0)
1338 if (stv090x_set_vit_thtracq(state) < 0)
1345 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1348 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1352 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1355 if (stv090x_vitclk_ctl(state, 0) < 0)
1358 if (stv090x_dvbs_track_crl(state) < 0)
1361 if (state->internal->dev_ver <= 0x20) {
1363 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x26) < 0)
1367 if (STV090x_WRITE_DEMOD(state, CAR2CFG, 0x66) < 0)
1371 if (state->demod_mode != STV090x_SINGLE) {
1373 if (stv090x_activate_modcod(state) < 0)
1380 if (stv090x_activate_modcod_single(state) < 0)
1384 if (stv090x_set_vit_thacq(state) < 0)
1387 if (stv090x_set_viterbi(state) < 0)
1397 static int stv090x_start_search(struct stv090x_state *state)
1403 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1405 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1408 if (state->internal->dev_ver <= 0x20) {
1409 if (state->srate <= 5000000) {
1410 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x44) < 0)
1412 if (STV090x_WRITE_DEMOD(state, CFRUP1, 0x0f) < 0)
1414 if (STV090x_WRITE_DEMOD(state, CFRUP0, 0xff) < 0)
1416 if (STV090x_WRITE_DEMOD(state, CFRLOW1, 0xf0) < 0)
1418 if (STV090x_WRITE_DEMOD(state, CFRLOW0, 0x00) < 0)
1422 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0)
1427 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1430 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
1435 if (state->srate <= 5000000) {
1437 STV090x_WRITE_DEMOD(state, RTCS2, 0x68);
1440 STV090x_WRITE_DEMOD(state, RTCS2, 0x44);
1444 STV090x_WRITE_DEMOD(state, CARCFG, 0x46);
1446 if (state->algo == STV090x_WARM_SEARCH) {
1452 freq_abs /= (state->internal->mclk / 1000);
1460 freq_abs = (state->search_range / 2000) + 600;
1462 freq_abs /= (state->internal->mclk / 1000);
1466 if (STV090x_WRITE_DEMOD(state, CFRUP1, MSB(freq)) < 0)
1468 if (STV090x_WRITE_DEMOD(state, CFRUP0, LSB(freq)) < 0)
1473 if (STV090x_WRITE_DEMOD(state, CFRLOW1, MSB(freq)) < 0)
1475 if (STV090x_WRITE_DEMOD(state, CFRLOW0, LSB(freq)) < 0)
1480 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0) < 0)
1482 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0) < 0)
1485 if (state->internal->dev_ver >= 0x20) {
1486 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
1488 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
1491 if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
1492 (state->search_mode == STV090x_SEARCH_DSS) ||
1493 (state->search_mode == STV090x_SEARCH_AUTO)) {
1495 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
1497 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0)
1502 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00) < 0)
1504 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xe0) < 0)
1506 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xc0) < 0)
1509 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1512 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1514 reg = STV090x_READ_DEMOD(state, DMDCFG2);
1516 if (STV090x_WRITE_DEMOD(state, DMDCFG2, reg) < 0)
1519 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0)
1522 if (state->internal->dev_ver >= 0x20) {
1524 if (state->srate < 2000000) {
1525 if (state->internal->dev_ver <= 0x20) {
1527 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x39) < 0)
1531 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x89) < 0)
1534 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x40) < 0)
1536 } else if (state->srate < 10000000) {
1537 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4c) < 0)
1539 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1542 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x4b) < 0)
1544 if (STV090x_WRITE_DEMOD(state, CARHDR, 0x20) < 0)
1548 if (state->srate < 10000000) {
1549 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xef) < 0)
1552 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0xed) < 0)
1557 switch (state->algo) {
1562 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1564 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
1570 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
1572 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
1585 static int stv090x_get_agc2_min_level(struct stv090x_state *state)
1590 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1592 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1595 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1598 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0) /* SR = 65 Msps Max */
1600 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1602 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0) /* SR= 400 ksps Min */
1604 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1606 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0) /* stop acq @ coarse carrier state */
1608 if (stv090x_set_srate(state, 1000000) < 0)
1611 steps = state->search_range / 1000000;
1616 freq_step = (1000000 * 256) / (state->internal->mclk / 256);
1627 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod RESET */
1629 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_init >> 8) & 0xff) < 0)
1631 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_init & 0xff) < 0)
1633 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x58) < 0) /* Demod RESET */
1639 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1640 STV090x_READ_DEMOD(state, AGC2I0);
1653 static u32 stv090x_get_srate(struct stv090x_state *state, u32 clk)
1658 r3 = STV090x_READ_DEMOD(state, SFR3);
1659 r2 = STV090x_READ_DEMOD(state, SFR2);
1660 r1 = STV090x_READ_DEMOD(state, SFR1);
1661 r0 = STV090x_READ_DEMOD(state, SFR0);
1678 static u32 stv090x_srate_srch_coarse(struct stv090x_state *state)
1680 struct dvb_frontend *fe = &state->frontend;
1687 if (state->internal->dev_ver >= 0x30)
1692 reg = STV090x_READ_DEMOD(state, DMDISTATE);
1694 if (STV090x_WRITE_DEMOD(state, DMDISTATE, reg) < 0)
1696 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0x12) < 0)
1698 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0)
1700 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0xf0) < 0)
1702 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0xe0) < 0)
1704 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1707 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1710 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x83) < 0)
1712 if (STV090x_WRITE_DEMOD(state, SFRUP0, 0xc0) < 0)
1714 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x82) < 0)
1716 if (STV090x_WRITE_DEMOD(state, SFRLOW0, 0xa0) < 0)
1718 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x00) < 0)
1720 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x50) < 0)
1723 if (state->internal->dev_ver >= 0x30) {
1724 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x99) < 0)
1726 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x98) < 0)
1729 } else if (state->internal->dev_ver >= 0x20) {
1730 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x6a) < 0)
1732 if (STV090x_WRITE_DEMOD(state, SFRSTEP, 0x95) < 0)
1736 if (state->srate <= 2000000)
1738 else if (state->srate <= 5000000)
1740 else if (state->srate <= 12000000)
1745 steps = -1 + ((state->search_range / 1000) / car_step);
1752 car_step = (state->search_range / 1000) / 10;
1756 freq = state->frequency;
1759 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5f) < 0) /* Demod RESET */
1761 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
1763 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
1765 if (STV090x_WRITE_DEMOD(state, SFRINIT1, 0x00) < 0)
1767 if (STV090x_WRITE_DEMOD(state, SFRINIT0, 0x00) < 0)
1770 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x40) < 0)
1774 reg = STV090x_READ_DEMOD(state, DSTATUS);
1777 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
1778 STV090x_READ_DEMOD(state, AGC2I0);
1781 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1794 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
1797 if (state->config->tuner_set_frequency) {
1798 if (state->config->tuner_set_frequency(fe, freq) < 0)
1802 if (state->config->tuner_set_bandwidth) {
1803 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
1807 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
1812 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
1815 if (state->config->tuner_get_status) {
1816 if (state->config->tuner_get_status(fe, ®) < 0)
1825 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
1833 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1838 stv090x_i2c_gate_ctrl(state, 0);
1844 static u32 stv090x_srate_srch_fine(struct stv090x_state *state)
1848 srate_coarse = stv090x_get_srate(state, state->internal->mclk);
1849 freq_coarse = STV090x_READ_DEMOD(state, CFR2) << 8;
1850 freq_coarse |= STV090x_READ_DEMOD(state, CFR1);
1853 if (sym < state->srate)
1856 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0) /* Demod RESET */
1858 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
1860 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
1862 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
1864 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
1866 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
1868 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
1871 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
1874 if (state->internal->dev_ver >= 0x30) {
1875 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x79) < 0)
1877 } else if (state->internal->dev_ver >= 0x20) {
1878 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
1885 sym /= (state->internal->mclk / 1000);
1886 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1888 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1892 sym /= (state->internal->mclk / 1000);
1893 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1895 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1898 sym /= (state->internal->mclk / 1000);
1899 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1901 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1906 sym /= (state->internal->mclk / 100);
1907 if (STV090x_WRITE_DEMOD(state, SFRUP1, (sym >> 8) & 0x7f) < 0)
1909 if (STV090x_WRITE_DEMOD(state, SFRUP0, sym & 0xff) < 0)
1913 sym /= (state->internal->mclk / 100);
1914 if (STV090x_WRITE_DEMOD(state, SFRLOW1, (sym >> 8) & 0x7f) < 0)
1916 if (STV090x_WRITE_DEMOD(state, SFRLOW0, sym & 0xff) < 0)
1919 sym /= (state->internal->mclk / 100);
1920 if (STV090x_WRITE_DEMOD(state, SFRINIT1, (sym >> 8) & 0xff) < 0)
1922 if (STV090x_WRITE_DEMOD(state, SFRINIT0, sym & 0xff) < 0)
1925 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
1927 if (STV090x_WRITE_DEMOD(state, CFRINIT1, (freq_coarse >> 8) & 0xff) < 0)
1929 if (STV090x_WRITE_DEMOD(state, CFRINIT0, freq_coarse & 0xff) < 0)
1931 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0) /* trigger acquisition */
1942 static int stv090x_get_dmdlock(struct stv090x_state *state, s32 timeout)
1949 reg = STV090x_READ_DEMOD(state, DMDSTATE);
1961 reg = STV090x_READ_DEMOD(state, DSTATUS);
1976 static int stv090x_blind_search(struct stv090x_state *state)
1987 agc2 = stv090x_get_agc2_min_level(state);
1989 if (agc2 > STV090x_SEARCH_AGC2_TH(state->internal->dev_ver)) {
1993 if (state->internal->dev_ver <= 0x20) {
1994 if (STV090x_WRITE_DEMOD(state, CARCFG, 0xc4) < 0)
1998 if (STV090x_WRITE_DEMOD(state, CARCFG, 0x06) < 0)
2002 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x44) < 0)
2005 if (state->internal->dev_ver >= 0x20) {
2006 if (STV090x_WRITE_DEMOD(state, EQUALCFG, 0x41) < 0)
2008 if (STV090x_WRITE_DEMOD(state, FFECFG, 0x41) < 0)
2010 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x82) < 0)
2012 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x00) < 0) /* set viterbi hysteresis */
2018 if (STV090x_WRITE_DEMOD(state, KREFTMG, k_ref) < 0)
2020 if (stv090x_srate_srch_coarse(state) != 0) {
2021 srate_coarse = stv090x_srate_srch_fine(state);
2023 stv090x_get_lock_tmg(state);
2024 lock = stv090x_get_dmdlock(state,
2025 state->DemodTimeout);
2033 agc2 += (STV090x_READ_DEMOD(state, AGC2I1) << 8) |
2034 STV090x_READ_DEMOD(state, AGC2I0);
2037 reg = STV090x_READ_DEMOD(state, DSTATUS2);
2059 static int stv090x_chk_tmg(struct stv090x_state *state)
2066 freq = STV090x_READ_DEMOD(state, CARFREQ);
2067 tmg_thh = STV090x_READ_DEMOD(state, TMGTHRISE);
2068 tmg_thl = STV090x_READ_DEMOD(state, TMGTHFALL);
2069 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, 0x20) < 0)
2071 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, 0x00) < 0)
2074 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2076 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2078 if (STV090x_WRITE_DEMOD(state, RTC, 0x80) < 0)
2081 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x40) < 0)
2083 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x00) < 0)
2086 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0) /* set car ofset to 0 */
2088 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
2090 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x65) < 0)
2093 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0) /* trigger acquisition */
2098 reg = STV090x_READ_DEMOD(state, DSTATUS);
2106 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2108 if (STV090x_WRITE_DEMOD(state, RTC, 0x88) < 0) /* DVB-S1 timing */
2110 if (STV090x_WRITE_DEMOD(state, RTCS2, 0x68) < 0) /* DVB-S2 timing */
2113 if (STV090x_WRITE_DEMOD(state, CARFREQ, freq) < 0)
2115 if (STV090x_WRITE_DEMOD(state, TMGTHRISE, tmg_thh) < 0)
2117 if (STV090x_WRITE_DEMOD(state, TMGTHFALL, tmg_thl) < 0)
2127 static int stv090x_get_coldlock(struct stv090x_state *state, s32 timeout_dmd)
2129 struct dvb_frontend *fe = &state->frontend;
2135 if (state->srate >= 10000000)
2140 lock = stv090x_get_dmdlock(state, timeout_lock); /* cold start wait */
2144 if (state->srate >= 10000000) {
2145 if (stv090x_chk_tmg(state)) {
2146 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2148 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2150 return stv090x_get_dmdlock(state, timeout_dmd);
2155 if (state->srate <= 4000000)
2157 else if (state->srate <= 7000000)
2159 else if (state->srate <= 10000000)
2164 steps = (state->search_range / 1000) / car_step;
2175 freq = state->frequency;
2176 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + state->srate;
2184 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
2187 if (state->config->tuner_set_frequency) {
2188 if (state->config->tuner_set_frequency(fe, freq) < 0)
2192 if (state->config->tuner_set_bandwidth) {
2193 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
2197 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
2202 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
2205 if (state->config->tuner_get_status) {
2206 if (state->config->tuner_get_status(fe, ®) < 0)
2214 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
2217 STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c);
2218 if (STV090x_WRITE_DEMOD(state, CFRINIT1, 0x00) < 0)
2220 if (STV090x_WRITE_DEMOD(state, CFRINIT0, 0x00) < 0)
2222 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
2224 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x15) < 0)
2226 lock = stv090x_get_dmdlock(state, (timeout_dmd / 3));
2235 stv090x_i2c_gate_ctrl(state, 0);
2241 static int stv090x_get_loop_params(struct stv090x_state *state, s32 *freq_inc, s32 *timeout_sw, s32 *steps)
2245 srate = state->srate;
2246 car_max = state->search_range / 1000;
2249 car_max /= (state->internal->mclk / 1000);
2255 inc /= state->internal->mclk / 1000;
2260 switch (state->search_mode) {
2301 static int stv090x_chk_signal(struct stv090x_state *state)
2306 offst_car = STV090x_READ_DEMOD(state, CFR2) << 8;
2307 offst_car |= STV090x_READ_DEMOD(state, CFR1);
2310 agc2 = STV090x_READ_DEMOD(state, AGC2I1) << 8;
2311 agc2 |= STV090x_READ_DEMOD(state, AGC2I0);
2312 car_max = state->search_range / 1000;
2316 car_max /= state->internal->mclk / 1000;
2332 static int stv090x_search_car_loop(struct stv090x_state *state, s32 inc, s32 timeout, int zigzag, s32 steps_max)
2338 car_max = state->search_range / 1000;
2341 car_max /= (state->internal->mclk / 1000);
2351 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1c) < 0)
2353 if (STV090x_WRITE_DEMOD(state, CFRINIT1, ((offst_freq / 256) & 0xff)) < 0)
2355 if (STV090x_WRITE_DEMOD(state, CFRINIT0, offst_freq & 0xff) < 0)
2357 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
2360 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2362 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2376 lock = stv090x_get_dmdlock(state, timeout);
2377 no_signal = stv090x_chk_signal(state);
2385 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
2387 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
2396 static int stv090x_sw_algo(struct stv090x_state *state)
2405 stv090x_get_loop_params(state, &inc, &timeout_step, &steps_max);
2407 switch (state->search_mode) {
2411 if (state->internal->dev_ver >= 0x20) {
2412 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3B) < 0)
2416 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x49) < 0)
2422 if (state->internal->dev_ver >= 0x20) {
2423 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2427 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2435 if (state->internal->dev_ver >= 0x20) {
2436 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x3b) < 0)
2438 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2442 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0xc9) < 0)
2450 lock = stv090x_search_car_loop(state, inc, timeout_step, zigzag, steps_max);
2451 no_signal = stv090x_chk_signal(state);
2457 if (state->internal->dev_ver >= 0x20) {
2458 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
2460 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
2464 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2468 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2472 reg = STV090x_READ_DEMOD(state, DMDFLYW);
2479 if (state->internal->dev_ver >= 0x20) {
2480 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x79) < 0)
2484 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, 0x89) < 0)
2498 static enum stv090x_delsys stv090x_get_std(struct stv090x_state *state)
2503 reg = STV090x_READ_DEMOD(state, DMDSTATE);
2507 reg = STV090x_READ_DEMOD(state, FECM);
2520 static s32 stv090x_get_car_freq(struct stv090x_state *state, u32 mclk)
2524 derot = STV090x_READ_DEMOD(state, CFR2) << 16;
2525 derot |= STV090x_READ_DEMOD(state, CFR1) << 8;
2526 derot |= STV090x_READ_DEMOD(state, CFR0);
2543 static int stv090x_get_viterbi(struct stv090x_state *state)
2547 reg = STV090x_READ_DEMOD(state, VITCURPUN);
2552 state->fec = STV090x_PR12;
2556 state->fec = STV090x_PR23;
2560 state->fec = STV090x_PR34;
2564 state->fec = STV090x_PR56;
2568 state->fec = STV090x_PR67;
2572 state->fec = STV090x_PR78;
2576 state->fec = STV090x_PRERR;
2583 static enum stv090x_signal_state stv090x_get_sig_params(struct stv090x_state *state)
2585 struct dvb_frontend *fe = &state->frontend;
2593 if (state->algo == STV090x_BLIND_SEARCH) {
2594 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2595 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x5c);
2597 tmg = STV090x_READ_DEMOD(state, TMGREG2);
2602 state->delsys = stv090x_get_std(state);
2604 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
2607 if (state->config->tuner_get_frequency) {
2608 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2612 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
2615 offst_freq = stv090x_get_car_freq(state, state->internal->mclk) / 1000;
2616 state->frequency += offst_freq;
2618 if (stv090x_get_viterbi(state) < 0)
2621 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2622 state->modcod = STV090x_GETFIELD_Px(reg, DEMOD_MODCOD_FIELD);
2623 state->pilots = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) & 0x01;
2624 state->frame_len = STV090x_GETFIELD_Px(reg, DEMOD_TYPE_FIELD) >> 1;
2625 reg = STV090x_READ_DEMOD(state, TMGOBS);
2626 state->rolloff = STV090x_GETFIELD_Px(reg, ROLLOFF_STATUS_FIELD);
2627 reg = STV090x_READ_DEMOD(state, FECM);
2628 state->inversion = STV090x_GETFIELD_Px(reg, IQINV_FIELD);
2630 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000)) {
2632 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
2635 if (state->config->tuner_get_frequency) {
2636 if (state->config->tuner_get_frequency(fe, &state->frequency) < 0)
2640 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
2643 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2645 else if (abs(offst_freq) <= (stv090x_car_width(state->srate, state->rolloff) / 2000))
2648 if (abs(offst_freq) <= ((state->search_range / 2000) + 500))
2655 stv090x_i2c_gate_ctrl(state, 0);
2661 static u32 stv090x_get_tmgoffst(struct stv090x_state *state, u32 srate)
2665 offst_tmg = STV090x_READ_DEMOD(state, TMGREG2) << 16;
2666 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG1) << 8;
2667 offst_tmg |= STV090x_READ_DEMOD(state, TMGREG0);
2679 static u8 stv090x_optimize_carloop(struct stv090x_state *state, enum stv090x_modcod modcod, s32 pilots)
2685 if (state->internal->dev_ver == 0x20) {
2721 if (state->srate <= 3000000)
2723 else if (state->srate <= 7000000)
2725 else if (state->srate <= 15000000)
2727 else if (state->srate <= 25000000)
2732 if (state->srate <= 3000000)
2734 else if (state->srate <= 7000000)
2736 else if (state->srate <= 15000000)
2738 else if (state->srate <= 25000000)
2746 if (state->srate <= 3000000)
2748 else if (state->srate <= 7000000)
2750 else if (state->srate <= 15000000)
2752 else if (state->srate <= 25000000)
2757 if (state->srate <= 3000000)
2759 else if (state->srate <= 7000000)
2761 else if (state->srate <= 15000000)
2763 else if (state->srate <= 25000000)
2775 if (state->srate <= 3000000)
2777 else if (state->srate <= 7000000)
2779 else if (state->srate <= 15000000)
2781 else if (state->srate <= 25000000)
2790 static u8 stv090x_optimize_carloop_short(struct stv090x_state *state)
2796 switch (state->modulation) {
2812 if (state->internal->dev_ver >= 0x30) {
2820 if (state->srate <= 3000000)
2822 else if (state->srate <= 7000000)
2824 else if (state->srate <= 15000000)
2826 else if (state->srate <= 25000000)
2834 static int stv090x_optimize_track(struct stv090x_state *state)
2836 struct dvb_frontend *fe = &state->frontend;
2843 srate = stv090x_get_srate(state, state->internal->mclk);
2844 srate += stv090x_get_tmgoffst(state, srate);
2846 switch (state->delsys) {
2849 if (state->search_mode == STV090x_SEARCH_AUTO) {
2850 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2853 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2856 reg = STV090x_READ_DEMOD(state, DEMOD);
2857 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
2859 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
2862 if (state->internal->dev_ver >= 0x30) {
2863 if (stv090x_get_viterbi(state) < 0)
2866 if (state->fec == STV090x_PR12) {
2867 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x98) < 0)
2869 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2872 if (STV090x_WRITE_DEMOD(state, GAUSSR0, 0x18) < 0)
2874 if (STV090x_WRITE_DEMOD(state, CCIR0, 0x18) < 0)
2879 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
2884 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2887 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2889 if (state->internal->dev_ver >= 0x30) {
2890 if (STV090x_WRITE_DEMOD(state, ACLC, 0) < 0)
2892 if (STV090x_WRITE_DEMOD(state, BCLC, 0) < 0)
2895 if (state->frame_len == STV090x_LONG_FRAME) {
2896 reg = STV090x_READ_DEMOD(state, DMDMODCOD);
2899 aclc = stv090x_optimize_carloop(state, modcod, pilots);
2901 STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc);
2903 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2905 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2908 if ((state->demod_mode == STV090x_SINGLE) && (modcod > STV090x_8PSK_910)) {
2910 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2912 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2915 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2917 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2923 aclc = stv090x_optimize_carloop_short(state);
2924 if (state->modulation == STV090x_QPSK) {
2925 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, aclc) < 0)
2927 } else if (state->modulation == STV090x_8PSK) {
2928 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2930 if (STV090x_WRITE_DEMOD(state, ACLC2S28, aclc) < 0)
2932 } else if (state->modulation == STV090x_16APSK) {
2933 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2935 if (STV090x_WRITE_DEMOD(state, ACLC2S216A, aclc) < 0)
2937 } else if (state->modulation == STV090x_32APSK) {
2938 if (STV090x_WRITE_DEMOD(state, ACLC2S2Q, 0x2a) < 0)
2940 if (STV090x_WRITE_DEMOD(state, ACLC2S232A, aclc) < 0)
2945 STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67); /* PER */
2950 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2953 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2958 f_1 = STV090x_READ_DEMOD(state, CFR2);
2959 f_0 = STV090x_READ_DEMOD(state, CFR1);
2960 reg = STV090x_READ_DEMOD(state, TMGOBS);
2962 if (state->algo == STV090x_BLIND_SEARCH) {
2963 STV090x_WRITE_DEMOD(state, SFRSTEP, 0x00);
2964 reg = STV090x_READ_DEMOD(state, DMDCFGMD);
2967 if (STV090x_WRITE_DEMOD(state, DMDCFGMD, reg) < 0)
2969 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0)
2972 if (stv090x_set_srate(state, srate) < 0)
2976 if (stv090x_dvbs_track_crl(state) < 0)
2980 if (state->internal->dev_ver >= 0x20) {
2981 if ((state->search_mode == STV090x_SEARCH_DVBS1) ||
2982 (state->search_mode == STV090x_SEARCH_DSS) ||
2983 (state->search_mode == STV090x_SEARCH_AUTO)) {
2985 if (STV090x_WRITE_DEMOD(state, VAVSRVIT, 0x0a) < 0)
2987 if (STV090x_WRITE_DEMOD(state, VITSCALE, 0x00) < 0)
2992 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
2996 if (STV090x_WRITE_DEMOD(state, SFRUP1, 0x80) < 0)
2999 if (STV090x_WRITE_DEMOD(state, SFRLOW1, 0x80) < 0)
3002 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1) ||
3003 (state->srate < 10000000)) {
3005 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3007 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3009 state->tuner_bw = stv090x_car_width(srate, state->rolloff) + 10000000;
3011 if ((state->internal->dev_ver >= 0x20) || (blind_tune == 1)) {
3013 if (state->algo != STV090x_WARM_SEARCH) {
3015 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3018 if (state->config->tuner_set_bandwidth) {
3019 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
3023 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3028 if ((state->algo == STV090x_BLIND_SEARCH) || (state->srate < 10000000))
3033 stv090x_get_lock_tmg(state);
3035 if (!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) {
3036 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
3038 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3040 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3042 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
3047 while ((!(stv090x_get_dmdlock(state, (state->DemodTimeout / 2)))) && (i <= 2)) {
3049 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x1f) < 0)
3051 if (STV090x_WRITE_DEMOD(state, CFRINIT1, f_1) < 0)
3053 if (STV090x_WRITE_DEMOD(state, CFRINIT0, f_0) < 0)
3055 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x18) < 0)
3063 if (state->internal->dev_ver >= 0x20) {
3064 if (STV090x_WRITE_DEMOD(state, CARFREQ, 0x49) < 0)
3068 if ((state->delsys == STV090x_DVBS1) || (state->delsys == STV090x_DSS))
3069 stv090x_set_vit_thtracq(state);
3074 stv090x_i2c_gate_ctrl(state, 0);
3080 static int stv090x_get_feclock(struct stv090x_state *state, s32 timeout)
3086 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3097 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3102 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3114 static int stv090x_get_lock(struct stv090x_state *state, s32 timeout_dmd, s32 timeout_fec)
3120 lock = stv090x_get_dmdlock(state, timeout_dmd);
3122 lock = stv090x_get_feclock(state, timeout_fec);
3128 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3138 static int stv090x_set_s2rolloff(struct stv090x_state *state)
3142 if (state->internal->dev_ver <= 0x20) {
3144 reg = STV090x_READ_DEMOD(state, DEMOD);
3146 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3150 reg = STV090x_READ_DEMOD(state, DEMOD);
3152 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3162 static enum stv090x_signal_state stv090x_algo(struct stv090x_state *state)
3164 struct dvb_frontend *fe = &state->frontend;
3170 reg = STV090x_READ_DEMOD(state, TSCFGH);
3172 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3175 if (STV090x_WRITE_DEMOD(state, DMDISTATE, 0x5c) < 0) /* Demod stop */
3178 if (state->internal->dev_ver >= 0x20) {
3179 if (state->srate > 5000000) {
3180 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x9e) < 0)
3183 if (STV090x_WRITE_DEMOD(state, CORRELABS, 0x82) < 0)
3188 stv090x_get_lock_tmg(state);
3190 if (state->algo == STV090x_BLIND_SEARCH) {
3191 state->tuner_bw = 2 * 36000000; /* wide bw for unknown srate */
3192 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc0) < 0) /* wider srate scan */
3194 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
3196 if (stv090x_set_srate(state, 1000000) < 0) /* initial srate = 1Msps */
3200 if (STV090x_WRITE_DEMOD(state, DMDTOM, 0x20) < 0)
3202 if (STV090x_WRITE_DEMOD(state, TMGCFG, 0xd2) < 0)
3205 if (state->srate < 2000000) {
3207 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x63) < 0)
3211 if (STV090x_WRITE_DEMOD(state, CORRELMANT, 0x70) < 0)
3215 if (STV090x_WRITE_DEMOD(state, AGC2REF, 0x38) < 0)
3218 if (state->internal->dev_ver >= 0x20) {
3219 if (STV090x_WRITE_DEMOD(state, KREFTMG, 0x5a) < 0)
3221 if (state->algo == STV090x_COLD_SEARCH)
3222 state->tuner_bw = (15 * (stv090x_car_width(state->srate, state->rolloff) + 10000000)) / 10;
3223 else if (state->algo == STV090x_WARM_SEARCH)
3224 state->tuner_bw = stv090x_car_width(state->srate, state->rolloff) + 10000000;
3230 if (STV090x_WRITE_DEMOD(state, TMGCFG2, 0xc1) < 0) /* narrow srate scan */
3233 if (stv090x_set_srate(state, state->srate) < 0)
3236 if (stv090x_set_max_srate(state, state->internal->mclk,
3237 state->srate) < 0)
3239 if (stv090x_set_min_srate(state, state->internal->mclk,
3240 state->srate) < 0)
3243 if (state->srate >= 10000000)
3250 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3253 if (state->config->tuner_set_bbgain) {
3254 reg = state->config->tuner_bbgain;
3257 if (state->config->tuner_set_bbgain(fe, reg) < 0)
3261 if (state->config->tuner_set_frequency) {
3262 if (state->config->tuner_set_frequency(fe, state->frequency) < 0)
3266 if (state->config->tuner_set_bandwidth) {
3267 if (state->config->tuner_set_bandwidth(fe, state->tuner_bw) < 0)
3271 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3276 if (state->config->tuner_get_status) {
3277 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3279 if (state->config->tuner_get_status(fe, ®) < 0)
3281 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3293 agc1_power = MAKEWORD16(STV090x_READ_DEMOD(state, AGCIQIN1),
3294 STV090x_READ_DEMOD(state, AGCIQIN0));
3301 power_iq += (STV090x_READ_DEMOD(state, POWERI) +
3302 STV090x_READ_DEMOD(state, POWERQ)) >> 1;
3312 reg = STV090x_READ_DEMOD(state, DEMOD);
3313 STV090x_SETFIELD_Px(reg, SPECINV_CONTROL_FIELD, state->inversion);
3315 if (state->internal->dev_ver <= 0x20) {
3322 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
3325 if (stv090x_delivery_search(state) < 0)
3328 if (state->algo != STV090x_BLIND_SEARCH) {
3329 if (stv090x_start_search(state) < 0)
3337 if (state->algo == STV090x_BLIND_SEARCH)
3338 lock = stv090x_blind_search(state);
3340 else if (state->algo == STV090x_COLD_SEARCH)
3341 lock = stv090x_get_coldlock(state, state->DemodTimeout);
3343 else if (state->algo == STV090x_WARM_SEARCH)
3344 lock = stv090x_get_dmdlock(state, state->DemodTimeout);
3346 if ((!lock) && (state->algo == STV090x_COLD_SEARCH)) {
3348 if (stv090x_chk_tmg(state))
3349 lock = stv090x_sw_algo(state);
3354 signal_state = stv090x_get_sig_params(state);
3357 stv090x_optimize_track(state);
3359 if (state->internal->dev_ver >= 0x20) {
3363 reg = STV090x_READ_DEMOD(state, TSCFGH);
3365 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3371 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3375 if (STV090x_WRITE_DEMOD(state, TSCFGH, reg) < 0)
3379 lock = stv090x_get_lock(state, state->FecTimeout,
3380 state->FecTimeout);
3382 if (state->delsys == STV090x_DVBS2) {
3383 stv090x_set_s2rolloff(state);
3385 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3387 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
3390 reg = STV090x_READ_DEMOD(state, PDELCTRL2);
3392 if (STV090x_WRITE_DEMOD(state, PDELCTRL2, reg) < 0)
3395 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x67) < 0) /* PER */
3398 if (STV090x_WRITE_DEMOD(state, ERRCTRL1, 0x75) < 0)
3402 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0x00) < 0)
3405 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3409 stv090x_chk_signal(state);
3415 stv090x_i2c_gate_ctrl(state, 0);
3421 static int stv090x_set_pls(struct stv090x_state *state, u32 pls_code)
3424 if (STV090x_WRITE_DEMOD(state, PLROOT0, pls_code & 0xff) < 0)
3426 if (STV090x_WRITE_DEMOD(state, PLROOT1, (pls_code >> 8) & 0xff) < 0)
3428 if (STV090x_WRITE_DEMOD(state, PLROOT2, 0x04 | (pls_code >> 16)) < 0)
3436 static int stv090x_set_mis(struct stv090x_state *state, int mis)
3442 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3444 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3448 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
3450 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
3452 if (STV090x_WRITE_DEMOD(state, ISIENTRY, mis) < 0)
3454 if (STV090x_WRITE_DEMOD(state, ISIBITENA, 0xff) < 0)
3465 struct stv090x_state *state = fe->demodulator_priv;
3473 state->delsys = STV090x_DSS;
3476 state->delsys = STV090x_DVBS1;
3479 state->delsys = STV090x_DVBS2;
3485 state->frequency = props->frequency;
3486 state->srate = props->symbol_rate;
3487 state->search_mode = STV090x_SEARCH_AUTO;
3488 state->algo = STV090x_COLD_SEARCH;
3489 state->fec = STV090x_PRERR;
3490 if (state->srate > 10000000) {
3492 state->search_range = 10000000;
3495 state->search_range = 5000000;
3498 stv090x_set_pls(state, props->scrambling_sequence_index);
3499 stv090x_set_mis(state, props->stream_id);
3501 if (stv090x_algo(state) == STV090x_RANGEOK) {
3514 struct stv090x_state *state = fe->demodulator_priv;
3520 dstatus = STV090x_READ_DEMOD(state, DSTATUS);
3524 reg = STV090x_READ_DEMOD(state, DMDSTATE);
3537 reg = STV090x_READ_DEMOD(state, PDELSTATUS1);
3540 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3550 reg = STV090x_READ_DEMOD(state, VSTATUSVIT);
3553 reg = STV090x_READ_DEMOD(state, TSSTATUS);
3566 struct stv090x_state *state = fe->demodulator_priv;
3577 reg = STV090x_READ_DEMOD(state, ERRCNT22);
3580 reg = STV090x_READ_DEMOD(state, ERRCNT21);
3583 reg = STV090x_READ_DEMOD(state, ERRCNT20);
3588 count_4 = STV090x_READ_DEMOD(state, FBERCPT4);
3589 count_3 = STV090x_READ_DEMOD(state, FBERCPT3);
3590 count_2 = STV090x_READ_DEMOD(state, FBERCPT2);
3591 count_1 = STV090x_READ_DEMOD(state, FBERCPT1);
3592 count_0 = STV090x_READ_DEMOD(state, FBERCPT0);
3604 if (STV090x_WRITE_DEMOD(state, FBERCPT4, 0) < 0)
3606 if (STV090x_WRITE_DEMOD(state, ERRCTRL2, 0xc1) < 0)
3653 struct stv090x_state *state = fe->demodulator_priv;
3658 reg = STV090x_READ_DEMOD(state, AGCIQIN1);
3660 reg = STV090x_READ_DEMOD(state, AGCIQIN0);
3677 struct stv090x_state *state = fe->demodulator_priv;
3684 switch (state->delsys) {
3686 reg = STV090x_READ_DEMOD(state, DSTATUS);
3691 reg_1 = STV090x_READ_DEMOD(state, NNOSPLHT1);
3693 reg_0 = STV090x_READ_DEMOD(state, NNOSPLHT0);
3711 reg = STV090x_READ_DEMOD(state, DSTATUS);
3716 reg_1 = STV090x_READ_DEMOD(state, NOSDATAT1);
3718 reg_0 = STV090x_READ_DEMOD(state, NOSDATAT0);
3740 struct stv090x_state *state = fe->demodulator_priv;
3743 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3748 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3751 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3758 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3779 struct stv090x_state *state = fe->demodulator_priv;
3783 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3786 (state->config->diseqc_envelope_mode) ? 4 : 2);
3788 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3791 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3795 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3801 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3805 if (STV090x_WRITE_DEMOD(state, DISTXDATA, cmd->msg[i]) < 0)
3808 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3810 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3816 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3831 struct stv090x_state *state = fe->demodulator_priv;
3836 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3839 mode = (state->config->diseqc_envelope_mode) ? 5 : 3;
3842 mode = (state->config->diseqc_envelope_mode) ? 4 : 2;
3848 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3851 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3855 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3859 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3863 if (STV090x_WRITE_DEMOD(state, DISTXDATA, value) < 0)
3866 reg = STV090x_READ_DEMOD(state, DISTXCTL);
3868 if (STV090x_WRITE_DEMOD(state, DISTXCTL, reg) < 0)
3874 reg = STV090x_READ_DEMOD(state, DISTXSTATUS);
3888 struct stv090x_state *state = fe->demodulator_priv;
3894 reg = STV090x_READ_DEMOD(state, DISRX_ST0);
3901 reply->msg[i] = STV090x_READ_DEMOD(state, DISRXDATA);
3909 struct stv090x_state *state = fe->demodulator_priv;
3913 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
3916 if (state->config->tuner_sleep) {
3917 if (state->config->tuner_sleep(fe) < 0)
3921 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
3925 state->device == STV0900 ? "STV0900" : "STV0903",
3926 state->demod);
3928 mutex_lock(&state->internal->demod_lock);
3930 switch (state->demod) {
3933 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3935 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
3938 reg = stv090x_read_reg(state, STV090x_TSTTNR2);
3940 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
3945 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
3950 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
3959 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
3961 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
3970 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
3976 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
3978 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
3981 reg = stv090x_read_reg(state, STV090x_TSTTNR4);
3983 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
3988 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
3993 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
4002 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4004 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
4013 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4024 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4026 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
4030 mutex_unlock(&state->internal->demod_lock);
4034 stv090x_i2c_gate_ctrl(state, 0);
4037 mutex_unlock(&state->internal->demod_lock);
4045 struct stv090x_state *state = fe->demodulator_priv;
4049 state->device == STV0900 ? "STV0900" : "STV0903",
4050 state->demod);
4052 mutex_lock(&state->internal->demod_lock);
4055 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4057 if (stv090x_write_reg(state, STV090x_SYNTCTRL, reg) < 0)
4060 switch (state->demod) {
4063 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
4065 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
4068 reg = stv090x_read_reg(state, STV090x_TSTTNR2);
4070 if (stv090x_write_reg(state, STV090x_TSTTNR2, reg) < 0)
4074 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
4081 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4083 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
4090 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4096 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
4098 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
4101 reg = stv090x_read_reg(state, STV090x_TSTTNR4);
4103 if (stv090x_write_reg(state, STV090x_TSTTNR4, reg) < 0)
4107 reg = stv090x_read_reg(state, STV090x_STOPCLK1);
4114 if (stv090x_write_reg(state, STV090x_STOPCLK1, reg) < 0)
4116 reg = stv090x_read_reg(state, STV090x_STOPCLK2);
4123 if (stv090x_write_reg(state, STV090x_STOPCLK2, reg) < 0)
4132 mutex_unlock(&state->internal->demod_lock);
4135 mutex_unlock(&state->internal->demod_lock);
4142 struct stv090x_state *state = fe->demodulator_priv;
4144 state->internal->num_used--;
4145 if (state->internal->num_used <= 0) {
4149 remove_dev(state->internal);
4150 kfree(state->internal);
4153 kfree(state);
4156 static int stv090x_ldpc_mode(struct stv090x_state *state, enum stv090x_mode ldpc_mode)
4160 reg = stv090x_read_reg(state, STV090x_GENCFG);
4165 if ((state->demod_mode != STV090x_DUAL) || (STV090x_GETFIELD(reg, DDEMOD_FIELD) != 1)) {
4167 if (stv090x_write_reg(state, STV090x_GENCFG, 0x1d) < 0)
4170 state->demod_mode = STV090x_DUAL;
4172 reg = stv090x_read_reg(state, STV090x_TSTRES0);
4174 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4177 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4180 if (STV090x_WRITE_DEMOD(state, MODCODLST0, 0xff) < 0)
4182 if (STV090x_WRITE_DEMOD(state, MODCODLST1, 0xff) < 0)
4184 if (STV090x_WRITE_DEMOD(state, MODCODLST2, 0xff) < 0)
4186 if (STV090x_WRITE_DEMOD(state, MODCODLST3, 0xff) < 0)
4188 if (STV090x_WRITE_DEMOD(state, MODCODLST4, 0xff) < 0)
4190 if (STV090x_WRITE_DEMOD(state, MODCODLST5, 0xff) < 0)
4192 if (STV090x_WRITE_DEMOD(state, MODCODLST6, 0xff) < 0)
4195 if (STV090x_WRITE_DEMOD(state, MODCODLST7, 0xcc) < 0)
4197 if (STV090x_WRITE_DEMOD(state, MODCODLST8, 0xcc) < 0)
4199 if (STV090x_WRITE_DEMOD(state, MODCODLST9, 0xcc) < 0)
4201 if (STV090x_WRITE_DEMOD(state, MODCODLSTA, 0xcc) < 0)
4203 if (STV090x_WRITE_DEMOD(state, MODCODLSTB, 0xcc) < 0)
4205 if (STV090x_WRITE_DEMOD(state, MODCODLSTC, 0xcc) < 0)
4207 if (STV090x_WRITE_DEMOD(state, MODCODLSTD, 0xcc) < 0)
4210 if (STV090x_WRITE_DEMOD(state, MODCODLSTE, 0xff) < 0)
4212 if (STV090x_WRITE_DEMOD(state, MODCODLSTF, 0xcf) < 0)
4218 if (stv090x_stop_modcod(state) < 0)
4220 if (stv090x_activate_modcod_single(state) < 0)
4223 if (state->demod == STV090x_DEMODULATOR_1) {
4224 if (stv090x_write_reg(state, STV090x_GENCFG, 0x06) < 0) /* path 2 */
4227 if (stv090x_write_reg(state, STV090x_GENCFG, 0x04) < 0) /* path 1 */
4231 reg = stv090x_read_reg(state, STV090x_TSTRES0);
4233 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4236 if (stv090x_write_reg(state, STV090x_TSTRES0, reg) < 0)
4239 reg = STV090x_READ_DEMOD(state, PDELCTRL1);
4241 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
4244 if (STV090x_WRITE_DEMOD(state, PDELCTRL1, reg) < 0)
4256 static u32 stv090x_get_mclk(struct stv090x_state *state)
4258 const struct stv090x_config *config = state->config;
4262 div = stv090x_read_reg(state, STV090x_NCOARSE);
4263 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4269 static int stv090x_set_mclk(struct stv090x_state *state, u32 mclk, u32 clk)
4271 const struct stv090x_config *config = state->config;
4274 reg = stv090x_read_reg(state, STV090x_SYNTCTRL);
4279 reg = stv090x_read_reg(state, STV090x_NCOARSE);
4281 if (stv090x_write_reg(state, STV090x_NCOARSE, reg) < 0)
4284 state->internal->mclk = stv090x_get_mclk(state);
4287 div = state->internal->mclk / 704000;
4288 if (STV090x_WRITE_DEMOD(state, F22TX, div) < 0)
4290 if (STV090x_WRITE_DEMOD(state, F22RX, div) < 0)
4299 static int stv0900_set_tspath(struct stv090x_state *state)
4303 if (state->internal->dev_ver >= 0x20) {
4304 switch (state->config->ts1_mode) {
4307 switch (state->config->ts2_mode) {
4311 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
4316 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x06) < 0) /* Mux'd stream mode */
4318 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4320 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4322 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
4324 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4326 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
4328 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4337 switch (state->config->ts2_mode) {
4341 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4347 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0a) < 0)
4354 switch (state->config->ts1_mode) {
4357 switch (state->config->ts2_mode) {
4361 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
4366 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16);
4367 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4369 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4371 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4373 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4375 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, 0x14) < 0)
4377 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, 0x28) < 0)
4386 switch (state->config->ts2_mode) {
4390 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
4395 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12);
4402 switch (state->config->ts1_mode) {
4404 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4405 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4408 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4413 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4414 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4417 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4422 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4423 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4426 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4431 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4432 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts1_tei);
4435 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4443 switch (state->config->ts2_mode) {
4445 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4446 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4449 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4454 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4455 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4458 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4463 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4464 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4467 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4472 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4473 STV090x_SETFIELD_Px(reg, TSFIFO_TEIUPDATE_FIELD, state->config->ts2_tei);
4476 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4484 if (state->config->ts1_clk > 0) {
4487 switch (state->config->ts1_mode) {
4491 speed = state->internal->mclk /
4492 (state->config->ts1_clk / 4);
4500 speed = state->internal->mclk /
4501 (state->config->ts1_clk / 32);
4508 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4510 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4512 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
4516 if (state->config->ts2_clk > 0) {
4519 switch (state->config->ts2_mode) {
4523 speed = state->internal->mclk /
4524 (state->config->ts2_clk / 4);
4532 speed = state->internal->mclk /
4533 (state->config->ts2_clk / 32);
4540 reg = stv090x_read_reg(state, STV090x_P2_TSCFGM);
4542 if (stv090x_write_reg(state, STV090x_P2_TSCFGM, reg) < 0)
4544 if (stv090x_write_reg(state, STV090x_P2_TSSPEED, speed) < 0)
4548 reg = stv090x_read_reg(state, STV090x_P2_TSCFGH);
4550 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4553 if (stv090x_write_reg(state, STV090x_P2_TSCFGH, reg) < 0)
4556 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4558 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4561 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4570 static int stv0903_set_tspath(struct stv090x_state *state)
4574 if (state->internal->dev_ver >= 0x20) {
4575 switch (state->config->ts1_mode) {
4578 stv090x_write_reg(state, STV090x_TSGENERAL, 0x00);
4584 stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c);
4588 switch (state->config->ts1_mode) {
4591 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10);
4597 stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14);
4602 switch (state->config->ts1_mode) {
4604 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4607 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4612 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4615 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4620 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4623 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4628 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4631 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4639 if (state->config->ts1_clk > 0) {
4642 switch (state->config->ts1_mode) {
4646 speed = state->internal->mclk /
4647 (state->config->ts1_clk / 4);
4655 speed = state->internal->mclk /
4656 (state->config->ts1_clk / 32);
4663 reg = stv090x_read_reg(state, STV090x_P1_TSCFGM);
4665 if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0)
4667 if (stv090x_write_reg(state, STV090x_P1_TSSPEED, speed) < 0)
4671 reg = stv090x_read_reg(state, STV090x_P1_TSCFGH);
4673 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4676 if (stv090x_write_reg(state, STV090x_P1_TSCFGH, reg) < 0)
4687 struct stv090x_state *state = fe->demodulator_priv;
4688 const struct stv090x_config *config = state->config;
4691 if (state->internal->mclk == 0) {
4695 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
4703 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
4706 stv090x_set_mclk(state, 135000000, config->xtal); /* 135 Mhz */
4708 if (stv090x_write_reg(state, STV090x_SYNTCTRL,
4711 stv090x_get_mclk(state);
4719 if (stv090x_ldpc_mode(state, state->demod_mode) < 0)
4722 reg = STV090x_READ_DEMOD(state, TNRCFG2);
4723 STV090x_SETFIELD_Px(reg, TUN_IQSWAP_FIELD, state->inversion);
4724 if (STV090x_WRITE_DEMOD(state, TNRCFG2, reg) < 0)
4726 reg = STV090x_READ_DEMOD(state, DEMOD);
4727 STV090x_SETFIELD_Px(reg, ROLLOFF_CONTROL_FIELD, state->rolloff);
4728 if (STV090x_WRITE_DEMOD(state, DEMOD, reg) < 0)
4731 if (stv090x_i2c_gate_ctrl(state, 1) < 0)
4744 if (stv090x_i2c_gate_ctrl(state, 0) < 0)
4747 if (state->device == STV0900) {
4748 if (stv0900_set_tspath(state) < 0)
4751 if (stv0903_set_tspath(state) < 0)
4758 stv090x_i2c_gate_ctrl(state, 0);
4766 struct stv090x_state *state = fe->demodulator_priv;
4767 const struct stv090x_config *config = state->config;
4775 if (state->device == STV0900) {
4781 } else if (state->device == STV0903) {
4792 if (stv090x_write_reg(state, STV090x_P1_DMDISTATE, 0x5c) < 0)
4794 if (state->device == STV0900)
4795 if (stv090x_write_reg(state, STV090x_P2_DMDISTATE, 0x5c) < 0)
4801 if (stv090x_write_reg(state, STV090x_P1_TNRCFG, 0x6c) < 0)
4803 if (state->device == STV0900)
4804 if (stv090x_write_reg(state, STV090x_P2_TNRCFG, 0x6c) < 0)
4809 if (stv090x_write_reg(state, STV090x_P1_I2CRPT, reg) < 0)
4811 if (state->device == STV0900)
4812 if (stv090x_write_reg(state, STV090x_P2_I2CRPT, reg) < 0)
4815 if (stv090x_write_reg(state, STV090x_NCOARSE, 0x13) < 0) /* set PLL divider */
4818 if (stv090x_write_reg(state, STV090x_I2CCFG, 0x08) < 0) /* 1/41 oversampling */
4820 if (stv090x_write_reg(state, STV090x_SYNTCTRL, 0x20 | config->clk_mode) < 0) /* enable PLL */
4827 if (stv090x_write_reg(state, stv090x_initval[i].addr, stv090x_initval[i].data) < 0)
4831 state->internal->dev_ver = stv090x_read_reg(state, STV090x_MID);
4832 if (state->internal->dev_ver >= 0x20) {
4833 if (stv090x_write_reg(state, STV090x_TSGENERAL, 0x0c) < 0)
4839 if (stv090x_write_reg(state, stv090x_cut20_val[i].addr, stv090x_cut20_val[i].data) < 0)
4843 } else if (state->internal->dev_ver < 0x20) {
4845 state->internal->dev_ver);
4848 } else if (state->internal->dev_ver > 0x30) {
4851 state->internal->dev_ver);
4855 reg = stv090x_read_reg(state, STV090x_TSTTNR1);
4858 if (stv090x_write_reg(state, STV090x_TSTTNR1, reg) < 0)
4862 reg = stv090x_read_reg(state, STV090x_TSTTNR3);
4865 if (stv090x_write_reg(state, STV090x_TSTTNR3, reg) < 0)
4868 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x80) < 0)
4870 if (stv090x_write_reg(state, STV090x_TSTRES0, 0x00) < 0)
4882 struct stv090x_state *state = fe->demodulator_priv;
4889 return stv090x_write_reg(state, STV090x_GPIOxCFG(gpio), reg);
4892 static int stv090x_setup_compound(struct stv090x_state *state)
4896 temp_int = find_dev(state->i2c,
4897 state->config->address);
4899 if (temp_int && state->demod_mode == STV090x_DUAL) {
4900 state->internal = temp_int->internal;
4901 state->internal->num_used++;
4904 state->internal = kmalloc(sizeof(*state->internal), GFP_KERNEL);
4905 if (!state->internal)
4907 temp_int = append_internal(state->internal);
4909 kfree(state->internal);
4912 state->internal->num_used = 1;
4913 state->internal->mclk = 0;
4914 state->internal->dev_ver = 0;
4915 state->internal->i2c_adap = state->i2c;
4916 state->internal->i2c_addr = state->config->address;
4919 mutex_init(&state->internal->demod_lock);
4920 mutex_init(&state->internal->tuner_lock);
4922 if (stv090x_setup(&state->frontend) < 0) {
4928 if (state->internal->dev_ver >= 0x30)
4929 state->frontend.ops.info.caps |= FE_CAN_MULTISTREAM;
4932 if (state->config->diseqc_envelope_mode)
4933 stv090x_send_diseqc_burst(&state->frontend, SEC_MINI_A);
4935 state->config->set_gpio = stv090x_set_gpio;
4938 state->device == STV0900 ? "STV0900" : "STV0903",
4939 state->config->demod,
4940 state->internal->dev_ver);
4947 remove_dev(state->internal);
4948 kfree(state->internal);
4986 struct stv090x_state *state = i2c_get_clientdata(client);
4990 return &state->frontend;
4998 struct stv090x_state *state = NULL;
5000 state = kzalloc(sizeof(*state), GFP_KERNEL);
5001 if (!state) {
5006 state->verbose = &verbose;
5007 state->config = config;
5008 state->i2c = client->adapter;
5009 state->frontend.ops = stv090x_ops;
5010 state->frontend.demodulator_priv = state;
5011 state->demod = config->demod;
5013 state->demod_mode = config->demod_mode;
5014 state->device = config->device;
5016 state->rolloff = STV090x_RO_35;
5018 ret = stv090x_setup_compound(state);
5022 i2c_set_clientdata(client, state);
5030 kfree(state);
5036 struct stv090x_state *state = i2c_get_clientdata(client);
5038 stv090x_release(&state->frontend);
5046 struct stv090x_state *state = NULL;
5048 state = kzalloc(sizeof(*state), GFP_KERNEL);
5049 if (!state)
5052 state->verbose = &verbose;
5053 state->config = config;
5054 state->i2c = i2c;
5055 state->frontend.ops = stv090x_ops;
5056 state->frontend.demodulator_priv = state;
5057 state->demod = demod;
5059 state->demod_mode = config->demod_mode;
5060 state->device = config->device;
5062 state->rolloff = STV090x_RO_35;
5064 ret = stv090x_setup_compound(state);
5068 return &state->frontend;
5071 kfree(state);