Lines Matching defs:state
44 enum stv0367_cab_signal_type state;
59 enum stv0367_ter_signal_type state;
122 int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data)
126 .addr = state->config->demod_address,
135 state->config->demod_address, reg, data);
137 ret = i2c_transfer(state->i2c, &msg, 1);
140 __func__, state->config->demod_address, reg, data);
146 u8 stv0367_readreg(struct stv0367_state *state, u16 reg)
152 .addr = state->config->demod_address,
157 .addr = state->config->demod_address,
168 ret = i2c_transfer(state->i2c, msg, 2);
171 __func__, state->config->demod_address, reg, b1[0]);
175 state->config->demod_address, reg, b1[0]);
194 static void stv0367_writebits(struct stv0367_state *state, u32 label, u8 val)
198 reg = stv0367_readreg(state, (label >> 16) & 0xffff);
204 stv0367_writereg(state, (label >> 16) & 0xffff, reg);
219 static u8 stv0367_readbits(struct stv0367_state *state, u32 label)
226 val = stv0367_readreg(state, label >> 16);
243 static void stv0367_write_table(struct stv0367_state *state,
251 stv0367_writereg(state, deftab[i].addr, deftab[i].value);
256 static void stv0367_pll_setup(struct stv0367_state *state,
270 stv0367_writereg(state, R367TER_PLLMDIV, 0x1b);
271 stv0367_writereg(state, R367TER_PLLNDIV, 0xe8);
280 stv0367_writereg(state, R367TER_PLLMDIV, 0x2);
281 stv0367_writereg(state, R367TER_PLLNDIV, 0x1b);
284 stv0367_writereg(state, R367TER_PLLMDIV, 0xa);
285 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
290 stv0367_writereg(state, R367TER_PLLMDIV, 0x1);
291 stv0367_writereg(state, R367TER_PLLNDIV, 0x8);
294 stv0367_writereg(state, R367TER_PLLMDIV, 0xc);
295 stv0367_writereg(state, R367TER_PLLNDIV, 0x55);
300 stv0367_writereg(state, R367TER_PLLSETUP, 0x18);
303 static int stv0367_get_if_khz(struct stv0367_state *state, u32 *ifkhz)
305 if (state->auto_if_khz && state->fe.ops.tuner_ops.get_if_frequency) {
306 state->fe.ops.tuner_ops.get_if_frequency(&state->fe, ifkhz);
309 *ifkhz = state->config->if_khz;
316 struct stv0367_state *state = fe->demodulator_priv;
317 u8 tmp = stv0367_readreg(state, R367TER_I2CRPT);
329 stv0367_writereg(state, R367TER_I2CRPT, tmp);
434 static u32 stv0367ter_get_mclk(struct stv0367_state *state, u32 ExtClk_Hz)
441 if (stv0367_readbits(state, F367TER_BYPASS_PLLXN) == 0) {
442 n = (u32)stv0367_readbits(state, F367TER_PLL_NDIV);
446 m = (u32)stv0367_readbits(state, F367TER_PLL_MDIV);
450 p = (u32)stv0367_readbits(state, F367TER_PLL_PDIV);
466 static int stv0367ter_filt_coeff_init(struct stv0367_state *state,
473 freq = stv0367ter_get_mclk(state, DemodXtal);
485 stv0367_writebits(state, F367TER_IIR_CELL_NB, i - 1);
488 stv0367_writereg(state,
491 stv0367_writereg(state,
501 static void stv0367ter_agc_iir_lock_detect_set(struct stv0367_state *state)
505 stv0367_writebits(state, F367TER_LOCK_DETECT_LSB, 0x00);
508 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x00);
509 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
510 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
513 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x01);
514 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x06);
515 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x04);
518 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x02);
519 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
520 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
523 stv0367_writebits(state, F367TER_LOCK_DETECT_CHOICE, 0x03);
524 stv0367_writebits(state, F367TER_LOCK_DETECT_MSB, 0x01);
525 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_LSB, 0x00);
529 static int stv0367_iir_filt_init(struct stv0367_state *state, u8 Bandwidth,
534 stv0367_writebits(state, F367TER_NRST_IIR, 0);
538 if (!stv0367ter_filt_coeff_init(state,
544 if (!stv0367ter_filt_coeff_init(state,
550 if (!stv0367ter_filt_coeff_init(state,
559 stv0367_writebits(state, F367TER_NRST_IIR, 1);
564 static void stv0367ter_agc_iir_rst(struct stv0367_state *state)
571 com_n = stv0367_readbits(state, F367TER_COM_N);
573 stv0367_writebits(state, F367TER_COM_N, 0x07);
575 stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x00);
576 stv0367_writebits(state, F367TER_COM_AGC_ON, 0x00);
578 stv0367_writebits(state, F367TER_COM_SOFT_RSTN, 0x01);
579 stv0367_writebits(state, F367TER_COM_AGC_ON, 0x01);
581 stv0367_writebits(state, F367TER_COM_N, com_n);
608 stv0367_ter_signal_type stv0367ter_check_syr(struct stv0367_state *state)
616 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
621 SYR_var = stv0367_readbits(state, F367TER_SYR_LOCK);
636 stv0367_ter_signal_type stv0367ter_check_cpamp(struct stv0367_state *state,
665 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
669 CPAMPvalue = stv0367_readbits(state, F367TER_PPM_CPAMP_DIRECT);
685 stv0367ter_lock_algo(struct stv0367_state *state)
694 if (state == NULL)
701 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
703 if (state->config->if_iq_mode != 0)
704 stv0367_writebits(state, F367TER_COM_N, 0x07);
706 stv0367_writebits(state, F367TER_GUARD, 3);/* suggest 2k 1/4 */
707 stv0367_writebits(state, F367TER_MODE, 0);
708 stv0367_writebits(state, F367TER_SYR_TR_DIS, 0);
711 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
714 if (stv0367ter_check_syr(state) == FE_TER_NOSYMBOL)
719 mode = stv0367_readbits(state, F367TER_SYR_MODE);
720 if (stv0367ter_check_cpamp(state, mode) ==
731 tmp = stv0367_readreg(state, R367TER_SYR_STAT);
732 tmp2 = stv0367_readreg(state, R367TER_STATUS);
733 dprintk("state=%p\n", state);
737 tmp = stv0367_readreg(state, R367TER_PRVIT);
738 tmp2 = stv0367_readreg(state, R367TER_I2CRPT);
741 tmp = stv0367_readreg(state, R367TER_GAIN_SRC1);
747 /*guard=stv0367_readbits(state,F367TER_SYR_GUARD); */
756 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
757 stv0367_writereg(state, R367TER_CHC_CTL, 0x01);
761 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
762 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
771 stv0367_writebits(state, F367TER_RST_SFEC, 1);
772 stv0367_writebits(state, F367TER_RST_REEDSOLO, 1);
774 stv0367_writebits(state, F367TER_RST_SFEC, 0);
775 stv0367_writebits(state, F367TER_RST_REEDSOLO, 0);
777 u_var1 = stv0367_readbits(state, F367TER_LK);
778 u_var2 = stv0367_readbits(state, F367TER_PRF);
779 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
780 /* u_var4=stv0367_readbits(state,F367TER_TSFIFO_LINEOK); */
789 u_var1 = stv0367_readbits(state, F367TER_LK);
790 u_var2 = stv0367_readbits(state, F367TER_PRF);
791 u_var3 = stv0367_readbits(state, F367TER_TPS_LOCK);
792 /*u_var4=stv0367_readbits(state, F367TER_TSFIFO_LINEOK); */
805 guard = stv0367_readbits(state, F367TER_SYR_GUARD);
806 stv0367_writereg(state, R367TER_CHC_CTL, 0x11);
810 stv0367_writebits(state, F367TER_AUTO_LE_EN, 0);
811 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x1);*/
812 stv0367_writebits(state, F367TER_SYR_FILTER, 0);
816 stv0367_writebits(state, F367TER_AUTO_LE_EN, 1);
817 /*stv0367_writereg(state,R367TER_CHC_CTL, 0x11);*/
818 stv0367_writebits(state, F367TER_SYR_FILTER, 1);
826 if ((stv0367_readbits(state, F367TER_TPS_CONST) == 2) &&
828 (stv0367_readbits(state, F367TER_TPS_HPCODE) != 0)) {
829 stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0);
830 stv0367_writereg(state, R367TER_SFDLYSETM, 0x60);
831 stv0367_writereg(state, R367TER_SFDLYSETL, 0x0);
833 stv0367_writereg(state, R367TER_SFDLYSETH, 0x0);
836 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
841 u_var4 = stv0367_readbits(state, F367TER_TSFIFO_LINEOK);
850 while ((stv0367_readbits(state,F367TER_COM_USEGAINTRK)!=1) &&
851 (stv0367_readbits(state,F367TER_COM_AGCLOCK)!=1)&&(tempo<100)) {
852 ChipWaitOrAbort(state,1);
856 stv0367_writebits(state,F367TER_COM_N,0x17);
859 stv0367_writebits(state, F367TER_SYR_TR_DIS, 1);
867 static void stv0367ter_set_ts_mode(struct stv0367_state *state,
873 if (state == NULL)
876 stv0367_writebits(state, F367TER_TS_DIS, 0);
881 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 0);
882 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 0);
885 stv0367_writebits(state, F367TER_TSFIFO_SERIAL, 1);
886 stv0367_writebits(state, F367TER_TSFIFO_DVBCI, 1);
891 static void stv0367ter_set_clk_pol(struct stv0367_state *state,
897 if (state == NULL)
902 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 1);
905 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
909 stv0367_writebits(state, F367TER_TS_BYTE_CLK_INV, 0);
915 static void stv0367ter_core_sw(struct stv0367_state *state)
920 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
921 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
927 struct stv0367_state *state = fe->demodulator_priv;
932 stv0367_writebits(state, F367TER_STDBY, 1);
933 stv0367_writebits(state, F367TER_STDBY_FEC, 1);
934 stv0367_writebits(state, F367TER_STDBY_CORE, 1);
936 stv0367_writebits(state, F367TER_STDBY, 0);
937 stv0367_writebits(state, F367TER_STDBY_FEC, 0);
938 stv0367_writebits(state, F367TER_STDBY_CORE, 0);
951 struct stv0367_state *state = fe->demodulator_priv;
952 struct stv0367ter_state *ter_state = state->ter_state;
958 stv0367_write_table(state,
959 stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
961 stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
963 stv0367_writereg(state, R367TER_I2CRPT, 0xa0);
964 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
967 stv0367ter_set_ts_mode(state, state->config->ts_mode);
968 stv0367ter_set_clk_pol(state, state->config->clk_pol);
970 state->chip_id = stv0367_readreg(state, R367TER_ID);
980 struct stv0367_state *state = fe->demodulator_priv;
981 struct stv0367ter_state *ter_state = state->ter_state;
991 stv0367_get_if_khz(state, &ifkhz);
995 + stv0367_readbits(state, F367TER_FORCE) * 2;
996 ter_state->if_iq_mode = state->config->if_iq_mode;
997 switch (state->config->if_iq_mode) {
1000 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1001 stv0367_writebits(state, F367TER_LONGPATH_IF, 0);
1002 stv0367_writebits(state, F367TER_DEMUX_SWAP, 0);
1006 stv0367_writebits(state, F367TER_TUNER_BB, 0);
1007 stv0367_writebits(state, F367TER_LONGPATH_IF, 1);
1008 stv0367_writebits(state, F367TER_DEMUX_SWAP, 1);
1012 stv0367_writebits(state, F367TER_TUNER_BB, 1);
1013 stv0367_writebits(state, F367TER_PPM_INVSEL, 0);
1027 stv0367_writebits(state, F367TER_IQ_INVERT,
1030 stv0367_writebits(state, F367TER_INV_SPECTR,
1037 stv0367_writebits(state, F367TER_IQ_INVERT,
1040 stv0367_writebits(state, F367TER_INV_SPECTR,
1048 stv0367ter_agc_iir_lock_detect_set(state);
1052 stv0367_writebits(state, F367TER_SEL_IQNTAR, 1);
1053 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1054 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1057 stv0367_writebits(state, F367TER_SEL_IQNTAR, 0);
1058 stv0367_writebits(state, F367TER_AUT_AGC_TARGET_MSB, 0xB);
1059 /*stv0367_writebits(state,AUT_AGC_TARGET_LSB,0x04); */
1061 if (!stv0367_iir_filt_init(state, ter_state->bw,
1062 state->config->xtal))
1067 stv0367ter_agc_iir_rst(state);
1071 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x01);
1073 stv0367_writebits(state, F367TER_BDI_LPSEL, 0x00);
1075 InternalFreq = stv0367ter_get_mclk(state, state->config->xtal) / 1000;
1080 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB, temp % 2);
1082 stv0367_writebits(state, F367TER_TRL_NOMRATE_HI, temp / 256);
1083 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO, temp % 256);
1085 temp = stv0367_readbits(state, F367TER_TRL_NOMRATE_HI) * 512 +
1086 stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2 +
1087 stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB);
1089 stv0367_writebits(state, F367TER_GAIN_SRC_HI, temp / 256);
1090 stv0367_writebits(state, F367TER_GAIN_SRC_LO, temp % 256);
1091 temp = stv0367_readbits(state, F367TER_GAIN_SRC_HI) * 256 +
1092 stv0367_readbits(state, F367TER_GAIN_SRC_LO);
1098 stv0367_writebits(state, F367TER_INC_DEROT_HI, temp / 256);
1099 stv0367_writebits(state, F367TER_INC_DEROT_LO, temp % 256);
1104 stv0367_writebits(state, F367TER_LONG_ECHO, ter_state->echo_pos);
1106 if (stv0367ter_lock_algo(state) != FE_TER_LOCKOK)
1109 ter_state->state = FE_TER_LOCKOK;
1111 ter_state->mode = stv0367_readbits(state, F367TER_SYR_MODE);
1112 ter_state->guard = stv0367_readbits(state, F367TER_SYR_GUARD);
1117 (stv0367_readbits(state, F367TER_AGC1_VAL_LO) << 16) +
1118 (stv0367_readbits(state, F367TER_AGC1_VAL_HI) << 24) +
1119 stv0367_readbits(state, F367TER_AGC2_VAL_LO) +
1120 (stv0367_readbits(state, F367TER_AGC2_VAL_HI) << 8);
1123 stv0367_writebits(state, F367TER_FREEZE, 1);
1124 offset = (stv0367_readbits(state, F367TER_CRL_FOFFSET_VHI) << 16) ;
1125 offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_HI) << 8);
1126 offset += (stv0367_readbits(state, F367TER_CRL_FOFFSET_LO));
1127 stv0367_writebits(state, F367TER_FREEZE, 0);
1140 if (stv0367_readbits(state, F367TER_PPM_INVSEL) == 1) {
1141 if ((stv0367_readbits(state, F367TER_INV_SPECTR) ==
1142 (stv0367_readbits(state,
1158 timing_offset = stv0367_readbits(state, F367TER_TRL_TOFFSET_LO)
1159 + 256 * stv0367_readbits(state,
1163 trl_nomrate = (512 * stv0367_readbits(state,
1165 + stv0367_readbits(state, F367TER_TRL_NOMRATE_LO) * 2
1166 + stv0367_readbits(state, F367TER_TRL_NOMRATE_LSB));
1183 stv0367_writebits(state, F367TER_TRL_NOMRATE_LSB,
1185 stv0367_writebits(state, F367TER_TRL_NOMRATE_LO,
1193 u_var = stv0367_readbits(state, F367TER_LK);
1196 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1198 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1207 struct stv0367_state *state = fe->demodulator_priv;
1208 struct stv0367ter_state *ter_state = state->ter_state;
1214 if (state->reinit_on_setfrontend)
1218 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
1221 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
1278 ter_state->state = FE_TER_NOLOCK;
1281 while (((index) < num_trials) && (ter_state->state != FE_TER_LOCKOK)) {
1289 if ((ter_state->state == FE_TER_LOCKOK) &&
1305 struct stv0367_state *state = fe->demodulator_priv;
1306 struct stv0367ter_state *ter_state = state->ter_state;
1310 if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0) {
1312 ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1314 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1316 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1328 struct stv0367_state *state = fe->demodulator_priv;
1329 struct stv0367ter_state *ter_state = state->ter_state;
1337 constell = stv0367_readbits(state, F367TER_TPS_CONST);
1345 p->inversion = stv0367_readbits(state, F367TER_INV_SPECTR);
1348 Data = stv0367_readbits(state, F367TER_TPS_HIERMODE);
1370 Data = stv0367_readbits(state, F367TER_TPS_LPCODE);
1372 Data = stv0367_readbits(state, F367TER_TPS_HPCODE);
1395 mode = stv0367_readbits(state, F367TER_SYR_MODE);
1411 p->guard_interval = stv0367_readbits(state, F367TER_SYR_GUARD);
1418 struct stv0367_state *state = fe->demodulator_priv;
1421 u8 cut = stv0367_readbits(state, F367TER_IDENTIFICATIONREG);
1426 snru32 += stv0367_readbits(state, F367TER_CHCSNR) / 4;
1428 snru32 += 125 * stv0367_readbits(state, F367TER_CHCSNR);
1450 struct stv0367_state *state = fe->demodulator_priv;
1451 struct stv0367ter_state *ter_state = state->ter_state;
1454 locked = (stv0367_readbits(state, F367TER_LK));
1461 if (!stv0367_readbits(state, F367TER_TPS_LOCK) ||
1462 (!stv0367_readbits(state, F367TER_LK))) {
1463 stv0367_writebits(state, F367TER_CORE_ACTIVE, 0);
1465 stv0367_writebits(state, F367TER_CORE_ACTIVE, 1);
1467 locked = (stv0367_readbits(state, F367TER_TPS_LOCK)) &&
1468 (stv0367_readbits(state, F367TER_LK));
1479 struct stv0367_state *state = fe->demodulator_priv;
1485 if (stv0367_readbits(state, F367TER_LK)) {
1496 struct stv0367_state *state = fe->demodulator_priv;
1497 struct stv0367ter_state *ter_state = state->ter_state;
1503 if (stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 0)
1504 Errors = ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT)
1506 + ((u32)stv0367_readbits(state, F367TER_SFEC_ERR_CNT_HI)
1508 + ((u32)stv0367_readbits(state,
1516 abc = stv0367_readbits(state, F367TER_SFEC_ERR_SOURCE);
1517 def = stv0367_readbits(state, F367TER_SFEC_NUM_EVENT);
1577 static u32 stv0367ter_get_per(struct stv0367_state *state)
1579 struct stv0367ter_state *ter_state = state->ter_state;
1583 while (((stv0367_readbits(state, F367TER_SFERRC_OLDVALUE) == 1) &&
1586 Errors = ((u32)stv0367_readbits(state, F367TER_ERR_CNT1)
1588 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_HI)
1590 + ((u32)stv0367_readbits(state, F367TER_ERR_CNT1_LO));
1593 abc = stv0367_readbits(state, F367TER_ERR_SRC1);
1594 def = stv0367_readbits(state, F367TER_NUM_EVT1);
1657 struct stv0367_state *state = fe->demodulator_priv;
1659 kfree(state->ter_state);
1660 kfree(state->cab_state);
1661 kfree(state);
1697 struct stv0367_state *state = NULL;
1700 /* allocate memory for the internal state */
1701 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
1702 if (state == NULL)
1708 /* setup the state */
1709 state->i2c = i2c;
1710 state->config = config;
1711 state->ter_state = ter_state;
1712 state->fe.ops = stv0367ter_ops;
1713 state->fe.demodulator_priv = state;
1714 state->chip_id = stv0367_readreg(state, 0xf000);
1717 state->use_i2c_gatectrl = 1;
1718 state->deftabs = STV0367_DEFTAB_GENERIC;
1719 state->reinit_on_setfrontend = 1;
1720 state->auto_if_khz = 0;
1722 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
1725 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
1728 return &state->fe;
1732 kfree(state);
1739 struct stv0367_state *state = fe->demodulator_priv;
1743 stv0367_writebits(state, F367CAB_I2CT_ON, (enable > 0) ? 1 : 0);
1750 struct stv0367_state *state = fe->demodulator_priv;
1755 if (stv0367_readbits(state, F367CAB_BYPASS_PLLXN) == 0) {
1756 N = (u32)stv0367_readbits(state, F367CAB_PLL_NDIV);
1760 M = (u32)stv0367_readbits(state, F367CAB_PLL_MDIV);
1764 P = (u32)stv0367_readbits(state, F367CAB_PLL_PDIV);
1785 static enum stv0367cab_mod stv0367cab_SetQamSize(struct stv0367_state *state,
1790 stv0367_writebits(state, F367CAB_QAM_MODE, QAMSize);
1795 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1798 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64);
1799 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1800 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
1801 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1802 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1803 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
1804 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1805 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a);
1808 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1809 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e);
1810 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
1811 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1812 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7);
1813 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d);
1814 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
1815 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1818 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82);
1819 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
1821 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0);
1822 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1823 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5);
1825 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1826 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1827 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
1829 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1830 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
1831 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1833 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95);
1834 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1835 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99);
1838 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1839 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76);
1840 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90);
1841 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1);
1843 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1845 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6);
1847 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97);
1849 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e);
1850 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f);
1851 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1854 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94);
1855 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a);
1856 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0);
1858 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1860 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1);
1862 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1);
1864 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7);
1865 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85);
1866 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40);
1867 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7);
1870 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1873 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00);
1882 static u32 stv0367cab_set_derot_freq(struct stv0367_state *state,
1908 stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if);
1909 stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8));
1910 stv0367_writebits(state, F367CAB_MIX_NCO_INC_HH, (sampled_if >> 16));
1915 static u32 stv0367cab_get_derot_freq(struct stv0367_state *state, u32 adc_hz)
1919 sampled_if = stv0367_readbits(state, F367CAB_MIX_NCO_INC_LL) +
1920 (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HL) << 8) +
1921 (stv0367_readbits(state, F367CAB_MIX_NCO_INC_HH) << 16);
1931 static u32 stv0367cab_set_srate(struct stv0367_state *state, u32 adc_hz,
1976 stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp);
2050 if (stv0367_readbits(state, F367CAB_ADJ_EN)) {
2051 stv0367cab_SetIirAdjacentcoefficient(state, mclk_hz,
2055 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 1);
2056 stv0367cab_SetAllPasscoefficient(state, mclk_hz, SymbolRate);
2061 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2063 stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp);
2064 stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8));
2065 stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16));
2066 stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24));
2068 stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff);
2069 stv0367_writebits(state, F367CAB_GAIN_SRC_HI, (u32_tmp1 >> 8) & 0x00ff);
2074 static u32 stv0367cab_GetSymbolRate(struct stv0367_state *state, u32 mclk_hz)
2079 regsym = stv0367_readreg(state, R367CAB_SRC_NCO_LL) +
2080 (stv0367_readreg(state, R367CAB_SRC_NCO_LH) << 8) +
2081 (stv0367_readreg(state, R367CAB_SRC_NCO_HL) << 16) +
2082 (stv0367_readreg(state, R367CAB_SRC_NCO_HH) << 24);
2119 static u32 stv0367cab_fsm_status(struct stv0367_state *state)
2121 return stv0367_readbits(state, F367CAB_FSM_STATUS);
2124 static u32 stv0367cab_qamfec_lock(struct stv0367_state *state)
2126 return stv0367_readbits(state,
2127 (state->cab_state->qamfec_status_reg ?
2128 state->cab_state->qamfec_status_reg :
2187 struct stv0367_state *state = fe->demodulator_priv;
2193 /* update cab_state->state from QAM_FSM_STATUS */
2194 state->cab_state->state = stv0367cab_fsm_signaltype(
2195 stv0367cab_fsm_status(state));
2197 if (stv0367cab_qamfec_lock(state)) {
2202 if (state->cab_state->state > FE_CAB_NOSIGNAL)
2205 if (state->cab_state->state > FE_CAB_NOCARRIER)
2208 if (state->cab_state->state >= FE_CAB_DEMODOK)
2211 if (state->cab_state->state >= FE_CAB_DATAOK)
2220 struct stv0367_state *state = fe->demodulator_priv;
2225 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x03);
2226 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x01);
2227 stv0367_writebits(state, F367CAB_STDBY, 1);
2228 stv0367_writebits(state, F367CAB_STDBY_CORE, 1);
2229 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 0);
2230 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 0);
2231 stv0367_writebits(state, F367CAB_POFFQ, 1);
2232 stv0367_writebits(state, F367CAB_POFFI, 1);
2234 stv0367_writebits(state, F367CAB_STDBY_PLLXN, 0x00);
2235 stv0367_writebits(state, F367CAB_BYPASS_PLLXN, 0x00);
2236 stv0367_writebits(state, F367CAB_STDBY, 0);
2237 stv0367_writebits(state, F367CAB_STDBY_CORE, 0);
2238 stv0367_writebits(state, F367CAB_EN_BUFFER_I, 1);
2239 stv0367_writebits(state, F367CAB_EN_BUFFER_Q, 1);
2240 stv0367_writebits(state, F367CAB_POFFQ, 0);
2241 stv0367_writebits(state, F367CAB_POFFI, 0);
2254 struct stv0367_state *state = fe->demodulator_priv;
2255 struct stv0367cab_state *cab_state = state->cab_state;
2259 stv0367_write_table(state,
2260 stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
2262 switch (state->config->ts_mode) {
2265 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x03);
2269 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x01);
2273 stv0367_writebits(state, F367CAB_OUTFORMAT, 0x00);
2277 switch (state->config->clk_pol) {
2279 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x00);
2283 stv0367_writebits(state, F367CAB_CLK_POLARITY, 0x01);
2287 stv0367_writebits(state, F367CAB_SYNC_STRIP, 0x00);
2289 stv0367_writebits(state, F367CAB_CT_NBST, 0x01);
2291 stv0367_writebits(state, F367CAB_TS_SWAP, 0x01);
2293 stv0367_writebits(state, F367CAB_FIFO_BYPASS, 0x00);
2295 stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */
2297 cab_state->mclk = stv0367cab_get_mclk(fe, state->config->xtal);
2298 cab_state->adc_clk = stv0367cab_get_adc_freq(fe, state->config->xtal);
2303 enum stv0367_cab_signal_type stv0367cab_algo(struct stv0367_state *state,
2306 struct stv0367cab_state *cab_state = state->cab_state;
2316 stv0367_get_if_khz(state, &ifkhz);
2384 stv0367_writereg(state, R367CAB_CTRL_1, 0x04);
2387 TrackAGCAccum = stv0367_readbits(state, F367CAB_AGC_ACCUMRSTSEL);
2388 stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, 0x0);
2390 stv0367_writebits(state, F367CAB_MODULUSMAP_EN, 0);
2392 stv0367_writebits(state, F367CAB_SWEEP_EN, 0);
2395 stv0367cab_set_derot_freq(state, cab_state->adc_clk,
2399 stv0367_writebits(state, F367CAB_ADJ_EN, 0);
2400 stv0367_writebits(state, F367CAB_ALLPASSFILT_EN, 0);
2411 stv0367_writereg(state, R367CAB_CTRL_1, 0x00);
2413 QAM_Lock = stv0367cab_fsm_status(state);
2430 u32_tmp = stv0367_readbits(state,
2432 (stv0367_readbits(state,
2434 (stv0367_readbits(state,
2438 u32_tmp = u32_tmp / (1 << (11 - stv0367_readbits(state,
2441 if (u32_tmp < stv0367_readbits(state,
2443 256 * stv0367_readbits(state,
2451 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2460 tmp = stv0367_readreg(state, R367CAB_IT_STATUS1);
2462 tmp = stv0367_readreg(state, R367CAB_IT_STATUS2);
2465 tmp = stv0367cab_get_derot_freq(state, cab_state->adc_clk);
2474 QAMFEC_Lock = stv0367cab_qamfec_lock(state);
2481 cab_state->spect_inv = stv0367_readbits(state,
2489 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2494 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2500 stv0367cab_get_derot_freq(state,
2505 cab_state->symbol_rate = stv0367cab_GetSymbolRate(state,
2509 /* stv0367_setbits(state, F367CAB_AGC_ACCUMRSTSEL,7);*/
2514 stv0367_writebits(state, F367CAB_AGC_ACCUMRSTSEL, TrackAGCAccum);
2521 struct stv0367_state *state = fe->demodulator_priv;
2522 struct stv0367cab_state *cab_state = state->cab_state;
2550 if (state->reinit_on_setfrontend)
2555 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
2558 if (state->use_i2c_gatectrl && fe->ops.i2c_gate_ctrl)
2563 state,
2567 stv0367cab_set_srate(state,
2573 cab_state->state = stv0367cab_algo(state, p);
2580 struct stv0367_state *state = fe->demodulator_priv;
2581 struct stv0367cab_state *cab_state = state->cab_state;
2588 stv0367_get_if_khz(state, &ifkhz);
2589 p->symbol_rate = stv0367cab_GetSymbolRate(state, cab_state->mclk);
2591 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
2618 (stv0367cab_get_derot_freq(state, cab_state->adc_clk) -
2625 - stv0367cab_get_derot_freq(state, cab_state->adc_clk)
2629 - stv0367cab_get_derot_freq(state, cab_state->adc_clk));
2635 void stv0367cab_GetErrorCount(state, enum stv0367cab_mod QAMSize,
2638 stv0367cab_OptimiseNByteAndGetBER(state, QAMSize, symbol_rate, Monitor_results);
2639 stv0367cab_GetPacketsCount(state, Monitor_results);
2646 struct stv0367_state *state = fe->demodulator_priv;
2651 static s32 stv0367cab_get_rf_lvl(struct stv0367_state *state)
2657 stv0367_writebits(state, F367CAB_STDBY_ADCGP, 0x0);
2660 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_LO) & 0x03) +
2661 (stv0367_readbits(state, F367CAB_RF_AGC1_LEVEL_HI) << 2);
2665 stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_LO) +
2666 (stv0367_readbits(state, F367CAB_AGC_IF_PWMCMD_HI) << 8);
2699 struct stv0367_state *state = fe->demodulator_priv;
2701 s32 signal = stv0367cab_get_rf_lvl(state);
2717 struct stv0367_state *state = fe->demodulator_priv;
2720 QAMSize = stv0367_readbits(state, F367CAB_QAM_MODE);
2745 struct stv0367_state *state = fe->demodulator_priv;
2750 regval += (stv0367_readbits(state, F367CAB_SNR_LO)
2751 + 256 * stv0367_readbits(state, F367CAB_SNR_HI));
2762 struct stv0367_state *state = fe->demodulator_priv;
2772 * (1 << (3 + stv0367_readbits(state, F367CAB_SNR_PER)));
2817 struct stv0367_state *state = fe->demodulator_priv;
2820 *ucblocks = (stv0367_readreg(state, R367CAB_RS_COUNTER_5) << 8)
2821 | stv0367_readreg(state, R367CAB_RS_COUNTER_4);
2822 corrected = (stv0367_readreg(state, R367CAB_RS_COUNTER_3) << 8)
2823 | stv0367_readreg(state, R367CAB_RS_COUNTER_2);
2824 tscount = (stv0367_readreg(state, R367CAB_RS_COUNTER_2) << 8)
2825 | stv0367_readreg(state, R367CAB_RS_COUNTER_1);
2864 struct stv0367_state *state = NULL;
2867 /* allocate memory for the internal state */
2868 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
2869 if (state == NULL)
2875 /* setup the state */
2876 state->i2c = i2c;
2877 state->config = config;
2880 state->cab_state = cab_state;
2881 state->fe.ops = stv0367cab_ops;
2882 state->fe.demodulator_priv = state;
2883 state->chip_id = stv0367_readreg(state, 0xf000);
2886 state->use_i2c_gatectrl = 1;
2887 state->deftabs = STV0367_DEFTAB_GENERIC;
2888 state->reinit_on_setfrontend = 1;
2889 state->auto_if_khz = 0;
2891 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
2894 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
2897 return &state->fe;
2901 kfree(state);
2910 static void stv0367ddb_setup_ter(struct stv0367_state *state)
2912 stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
2913 stv0367_writereg(state, R367TER_DEBUG_LT5, 0x00);
2914 stv0367_writereg(state, R367TER_DEBUG_LT6, 0x00); /* R367CAB_CTRL_1 */
2915 stv0367_writereg(state, R367TER_DEBUG_LT7, 0x00); /* R367CAB_CTRL_2 */
2916 stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
2917 stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
2921 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x89);
2922 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
2926 stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
2927 stv0367_writereg(state, R367TER_TOPCTRL, 0x00); /* Set OFDM */
2930 stv0367_pll_setup(state, STV0367_ICSPEED_53125, state->config->xtal);
2934 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
2936 state->activedemod = demod_ter;
2939 static void stv0367ddb_setup_cab(struct stv0367_state *state)
2941 stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00);
2942 stv0367_writereg(state, R367TER_DEBUG_LT5, 0x01);
2943 stv0367_writereg(state, R367TER_DEBUG_LT6, 0x06); /* R367CAB_CTRL_1 */
2944 stv0367_writereg(state, R367TER_DEBUG_LT7, 0x03); /* R367CAB_CTRL_2 */
2945 stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00);
2946 stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00);
2950 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8B);
2952 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04);
2956 stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
2958 stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
2961 stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
2965 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
2967 state->cab_state->mclk = stv0367cab_get_mclk(&state->fe,
2968 state->config->xtal);
2969 state->cab_state->adc_clk = stv0367cab_get_adc_freq(&state->fe,
2970 state->config->xtal);
2972 state->activedemod = demod_cab;
2977 struct stv0367_state *state = fe->demodulator_priv;
2981 if (state->activedemod != demod_ter)
2982 stv0367ddb_setup_ter(state);
2986 if (state->activedemod != demod_cab)
2987 stv0367ddb_setup_cab(state);
3005 struct stv0367_state *state = fe->demodulator_priv;
3009 switch (state->activedemod) {
3011 signalstrength = stv0367cab_get_rf_lvl(state) * 1000;
3024 struct stv0367_state *state = fe->demodulator_priv;
3029 switch (state->activedemod) {
3057 struct stv0367_state *state = fe->demodulator_priv;
3061 switch (state->activedemod) {
3080 struct stv0367_state *state = fe->demodulator_priv;
3084 switch (state->activedemod) {
3119 struct stv0367_state *state = fe->demodulator_priv;
3121 switch (state->activedemod) {
3135 struct stv0367_state *state = fe->demodulator_priv;
3137 switch (state->activedemod) {
3139 state->activedemod = demod_none;
3142 state->activedemod = demod_none;
3151 static int stv0367ddb_init(struct stv0367_state *state)
3153 struct stv0367ter_state *ter_state = state->ter_state;
3154 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;
3156 stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
3158 if (stv0367_deftabs[state->deftabs][STV0367_TAB_BASE])
3159 stv0367_write_table(state,
3160 stv0367_deftabs[state->deftabs][STV0367_TAB_BASE]);
3162 stv0367_write_table(state,
3163 stv0367_deftabs[state->deftabs][STV0367_TAB_CAB]);
3165 stv0367_writereg(state, R367TER_TOPCTRL, 0x00);
3166 stv0367_write_table(state,
3167 stv0367_deftabs[state->deftabs][STV0367_TAB_TER]);
3169 stv0367_writereg(state, R367TER_GAIN_SRC1, 0x2A);
3170 stv0367_writereg(state, R367TER_GAIN_SRC2, 0xD6);
3171 stv0367_writereg(state, R367TER_INC_DEROT1, 0x55);
3172 stv0367_writereg(state, R367TER_INC_DEROT2, 0x55);
3173 stv0367_writereg(state, R367TER_TRL_CTL, 0x14);
3174 stv0367_writereg(state, R367TER_TRL_NOMRATE1, 0xAE);
3175 stv0367_writereg(state, R367TER_TRL_NOMRATE2, 0x56);
3176 stv0367_writereg(state, R367TER_FEPATH_CFG, 0x0);
3180 stv0367_writereg(state, R367TER_TSCFGH, 0x70);
3181 stv0367_writereg(state, R367TER_TSCFGM, 0xC0);
3182 stv0367_writereg(state, R367TER_TSCFGL, 0x20);
3183 stv0367_writereg(state, R367TER_TSSPEED, 0x40); /* Fixed at 54 MHz */
3185 stv0367_writereg(state, R367TER_TSCFGH, 0x71);
3186 stv0367_writereg(state, R367TER_TSCFGH, 0x70);
3188 stv0367_writereg(state, R367TER_TOPCTRL, 0x10);
3191 stv0367_writereg(state, R367TER_AGC12C, 0x01); /* AGC Pin setup */
3193 stv0367_writereg(state, R367TER_AGCCTRL1, 0x8A);
3198 stv0367_writereg(state, R367CAB_OUTFORMAT_0, 0x85);
3201 stv0367_writereg(state, R367TER_ANACTRL, 0x0D);
3204 stv0367_pll_setup(state, STV0367_ICSPEED_58000, state->config->xtal);
3208 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8b);
3209 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */
3212 stv0367_writereg(state, R367CAB_FSM_SNR2_HTH, 0x23);
3214 stv0367_writereg(state, R367CAB_IQ_QAM, 0x01);
3216 stv0367_writereg(state, R367CAB_EQU_FFE_LEAKAGE, 0x83);
3218 stv0367_writereg(state, R367CAB_IQDEM_ADJ_EN, 0x05);
3221 stv0367_writereg(state, R367TER_ANACTRL, 0x00);
3223 stv0367_writereg(state, R367TER_I2CRPT, (0x08 | ((5 & 0x07) << 4)));
3272 struct stv0367_state *state = NULL;
3276 /* allocate memory for the internal state */
3277 state = kzalloc(sizeof(struct stv0367_state), GFP_KERNEL);
3278 if (state == NULL)
3287 /* setup the state */
3288 state->i2c = i2c;
3289 state->config = config;
3290 state->ter_state = ter_state;
3293 state->cab_state = cab_state;
3294 state->fe.ops = stv0367ddb_ops;
3295 state->fe.demodulator_priv = state;
3296 state->chip_id = stv0367_readreg(state, R367TER_ID);
3299 state->use_i2c_gatectrl = 0;
3300 state->deftabs = STV0367_DEFTAB_DDB;
3301 state->reinit_on_setfrontend = 0;
3302 state->auto_if_khz = 1;
3303 state->activedemod = demod_none;
3305 dprintk("%s: chip_id = 0x%x\n", __func__, state->chip_id);
3308 if ((state->chip_id != 0x50) && (state->chip_id != 0x60))
3312 state->fe.ops.info.name, state->chip_id,
3315 stv0367ddb_init(state);
3317 return &state->fe;
3322 kfree(state);