Lines Matching refs:state
138 static int i2cread(struct mxl *state, u8 *data, int len)
140 return i2c_read(state->base->i2c, state->base->adr, data, len);
143 static int i2cwrite(struct mxl *state, u8 *data, int len)
145 return i2c_write(state->base->i2c, state->base->adr, data, len);
148 static int read_register_unlocked(struct mxl *state, u32 reg, u32 *val)
157 stat = i2cwrite(state, data,
160 dev_err(state->i2cdev, "i2c read error 1\n");
162 stat = i2cread(state, (u8 *) val,
166 dev_err(state->i2cdev, "i2c read error 2\n");
173 static int send_command(struct mxl *state, u32 size, u8 *buf)
178 mutex_lock(&state->base->i2c_lock);
179 if (state->base->fwversion > 0x02010109) {
180 read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR, &val);
182 dev_info(state->i2cdev, "%s busy\n", __func__);
184 mutex_unlock(&state->base->i2c_lock);
186 mutex_lock(&state->base->i2c_lock);
187 read_register_unlocked(state, DMA_I2C_INTERRUPT_ADDR,
191 dev_info(state->i2cdev, "%s busy\n", __func__);
192 mutex_unlock(&state->base->i2c_lock);
196 stat = i2cwrite(state, buf, size);
197 mutex_unlock(&state->base->i2c_lock);
201 static int write_register(struct mxl *state, u32 reg, u32 val)
209 mutex_lock(&state->base->i2c_lock);
210 stat = i2cwrite(state, data, sizeof(data));
211 mutex_unlock(&state->base->i2c_lock);
213 dev_err(state->i2cdev, "i2c write error\n");
217 static int write_firmware_block(struct mxl *state,
221 u8 *buf = state->base->buf;
223 mutex_lock(&state->base->i2c_lock);
231 stat = i2cwrite(state, buf,
234 mutex_unlock(&state->base->i2c_lock);
236 dev_err(state->i2cdev, "fw block write failed\n");
240 static int read_register(struct mxl *state, u32 reg, u32 *val)
249 mutex_lock(&state->base->i2c_lock);
250 stat = i2cwrite(state, data,
253 dev_err(state->i2cdev, "i2c read error 1\n");
255 stat = i2cread(state, (u8 *) val,
257 mutex_unlock(&state->base->i2c_lock);
260 dev_err(state->i2cdev, "i2c read error 2\n");
264 static int read_register_block(struct mxl *state, u32 reg, u32 size, u8 *data)
267 u8 *buf = state->base->buf;
269 mutex_lock(&state->base->i2c_lock);
277 stat = i2cwrite(state, buf,
280 stat = i2cread(state, data, size);
283 mutex_unlock(&state->base->i2c_lock);
287 static int read_by_mnemonic(struct mxl *state,
293 stat = read_register(state, reg, &data);
304 static int update_by_mnemonic(struct mxl *state,
310 stat = read_register(state, reg, &data);
315 stat = write_register(state, reg, data);
319 static int firmware_is_alive(struct mxl *state)
323 if (read_register(state, HYDRA_HEAR_BEAT, &hb0))
326 if (read_register(state, HYDRA_HEAR_BEAT, &hb1))
356 struct mxl *state = fe->demodulator_priv;
358 list_del(&state->mxl);
360 state->base->count--;
361 if (state->base->count == 0) {
362 list_del(&state->base->mxllist);
363 kfree(state->base);
365 kfree(state);
384 static int cfg_scrambler(struct mxl *state, u32 gold)
390 state->demod, 0, 0, 0,
402 return send_command(state, sizeof(buf), buf);
405 static int cfg_demod_abort_tune(struct mxl *state)
411 abort_tune_cmd.demod_id = state->demod;
414 return send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
421 /*struct mxl *state = fe->demodulator_priv;*/
423 return 0; /*CfgDemodAbortTune(state);*/
428 struct mxl *state = fe->demodulator_priv;
441 /* CfgDemodAbortTune(state); */
462 cfg_scrambler(state, p->scrambling_sequence_index);
467 demod_chan_cfg.tuner_index = state->tuner;
468 demod_chan_cfg.demod_index = state->demod;
475 mutex_lock(&state->base->tune_lock);
477 state->base->next_tune))
478 while (time_before(jiffies, state->base->next_tune))
480 state->base->next_tune = jiffies + msecs_to_jiffies(100);
481 state->tuner_in_use = state->tuner;
484 stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
486 mutex_unlock(&state->base->tune_lock);
490 static int enable_tuner(struct mxl *state, u32 tuner, u32 enable);
494 struct mxl *state = fe->demodulator_priv;
497 cfg_demod_abort_tune(state);
498 if (state->tuner_in_use != 0xffffffff) {
499 mutex_lock(&state->base->tune_lock);
500 state->tuner_in_use = 0xffffffff;
501 list_for_each_entry(p, &state->base->mxls, mxl) {
502 if (p->tuner_in_use == state->tuner)
505 if (&p->mxl == &state->base->mxls)
506 enable_tuner(state, state->tuner, 0);
507 mutex_unlock(&state->base->tune_lock);
514 struct mxl *state = fe->demodulator_priv;
519 mutex_lock(&state->base->status_lock);
520 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
521 stat = read_register(state, (HYDRA_DMD_SNR_ADDR_OFFSET +
522 HYDRA_DMD_STATUS_OFFSET(state->demod)),
524 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
525 mutex_unlock(&state->base->status_lock);
535 struct mxl *state = fe->demodulator_priv;
539 mutex_lock(&state->base->status_lock);
540 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
541 read_register_block(state,
543 HYDRA_DMD_STATUS_OFFSET(state->demod)),
546 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
560 read_register_block(state,
562 HYDRA_DMD_STATUS_OFFSET(state->demod)),
584 mutex_unlock(&state->base->status_lock);
591 struct mxl *state = fe->demodulator_priv;
596 mutex_lock(&state->base->status_lock);
597 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
598 stat = read_register(state, (HYDRA_DMD_STATUS_INPUT_POWER_ADDR +
599 HYDRA_DMD_STATUS_OFFSET(state->demod)),
601 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
602 mutex_unlock(&state->base->status_lock);
612 struct mxl *state = fe->demodulator_priv;
616 mutex_lock(&state->base->status_lock);
617 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
618 read_register(state, (HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET +
619 HYDRA_DMD_STATUS_OFFSET(state->demod)),
621 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
622 mutex_unlock(&state->base->status_lock);
652 struct mxl *state = fe->demodulator_priv;
660 state->tune_time = jiffies;
682 struct mxl *state = fe->demodulator_priv;
686 mutex_lock(&state->base->status_lock);
687 HYDRA_DEMOD_STATUS_LOCK(state, state->demod);
688 read_register_block(state,
690 HYDRA_DMD_STATUS_OFFSET(state->demod)),
694 read_register_block(state,
696 HYDRA_DMD_STATUS_OFFSET(state->demod)),
699 HYDRA_DEMOD_STATUS_UNLOCK(state, state->demod);
700 mutex_unlock(&state->base->status_lock);
702 dev_dbg(state->i2cdev, "freq=%u delsys=%u srate=%u\n",
768 struct mxl *state = fe->demodulator_priv;
770 state->tuner = input;
807 static void cfg_dev_xtal(struct mxl *state, u32 freq, u32 cap, u32 enable)
809 if (state->base->can_clkout || !enable)
810 update_by_mnemonic(state, 0x90200054, 23, 1, enable);
813 write_register(state, HYDRA_CRYSTAL_SETTING, 0);
815 write_register(state, HYDRA_CRYSTAL_SETTING, 1);
817 write_register(state, HYDRA_CRYSTAL_CAP, cap);
841 static int write_fw_segment(struct mxl *state,
865 status = write_firmware_block(state, mem_addr, size, w_buf_ptr);
876 static int do_firmware_download(struct mxl *state, u8 *mbin_buffer_ptr,
889 dev_err(state->i2cdev, "%s: Invalid file header ID (%c)\n",
893 status = write_register(state, FW_DL_SIGN_ADDR, 0);
899 dev_err(state->i2cdev, "%s: Invalid segment header ID (%c)\n",
908 if (state->base->type == MXL_HYDRA_DEVICE_568) {
912 update_by_mnemonic(state, 0x8003003C, 0, 1, 1);
914 write_register(state, 0x90720000, 0);
918 status = write_fw_segment(state, seg_address,
924 status = write_fw_segment(state, seg_address,
935 static int check_fw(struct mxl *state, u8 *mbin, u32 mbin_len)
944 dev_info(state->i2cdev, "Invalid FW Header\n");
951 dev_info(state->i2cdev, "Invalid FW Checksum\n");
957 static int firmware_download(struct mxl *state, u8 *mbin, u32 mbin_len)
965 if (check_fw(state, mbin, mbin_len))
969 status = update_by_mnemonic(state, 0x8003003C, 0, 1, 0);
975 status = write_register(state, HYDRA_RESET_TRANSPORT_FIFO_REG,
979 status = write_register(state, HYDRA_RESET_BBAND_REG,
983 status = write_register(state, HYDRA_RESET_XBAR_REG,
991 status = write_register(state, HYDRA_MODULES_CLK_2_REG,
996 status = read_register(state, HYDRA_PRCM_ROOT_CLK_REG, ®_data);
999 status = do_firmware_download(state, mbin, mbin_len);
1003 if (state->base->type == MXL_HYDRA_DEVICE_568) {
1007 status = write_register(state, 0x90720000, 1);
1013 status = write_register(state, 0x9076B510, 1);
1018 status = update_by_mnemonic(state, 0x8003003C, 0, 1, 1);
1026 status = write_register(state, XPT_DMD0_BASEADDR, 0x76543210);
1030 if (!firmware_is_alive(state))
1033 dev_info(state->i2cdev, "Hydra FW alive. Hail!\n");
1040 dev_sku_cfg.sku_type = state->base->sku_type;
1043 status = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
1049 static int cfg_ts_pad_mux(struct mxl *state, enum MXL_BOOL_E enable_serial_ts)
1056 if ((state->base->type == MXL_HYDRA_DEVICE_541) ||
1057 (state->base->type == MXL_HYDRA_DEVICE_541S))
1060 if ((state->base->type == MXL_HYDRA_DEVICE_581) ||
1061 (state->base->type == MXL_HYDRA_DEVICE_581S))
1067 switch (state->base->type) {
1074 status |= update_by_mnemonic(state, 0x90000170, 24, 3,
1076 status |= update_by_mnemonic(state, 0x90000170, 28, 3,
1078 status |= update_by_mnemonic(state, 0x90000174, 0, 3,
1080 status |= update_by_mnemonic(state, 0x90000174, 4, 3,
1082 status |= update_by_mnemonic(state, 0x90000174, 8, 3,
1084 status |= update_by_mnemonic(state, 0x90000174, 12, 3,
1086 status |= update_by_mnemonic(state, 0x90000174, 16, 3,
1088 status |= update_by_mnemonic(state, 0x90000174, 20, 3,
1090 status |= update_by_mnemonic(state, 0x90000174, 24, 3,
1092 status |= update_by_mnemonic(state, 0x90000174, 28, 3,
1094 status |= update_by_mnemonic(state, 0x90000178, 0, 3,
1096 status |= update_by_mnemonic(state, 0x90000178, 4, 3,
1098 status |= update_by_mnemonic(state, 0x90000178, 8, 3,
1104 status |= update_by_mnemonic(state, 0x9000016C, 4, 3, 1);
1105 status |= update_by_mnemonic(state, 0x9000016C, 8, 3, 0);
1106 status |= update_by_mnemonic(state, 0x9000016C, 12, 3, 0);
1107 status |= update_by_mnemonic(state, 0x9000016C, 16, 3, 0);
1108 status |= update_by_mnemonic(state, 0x90000170, 0, 3, 0);
1109 status |= update_by_mnemonic(state, 0x90000178, 12, 3, 1);
1110 status |= update_by_mnemonic(state, 0x90000178, 16, 3, 1);
1111 status |= update_by_mnemonic(state, 0x90000178, 20, 3, 1);
1112 status |= update_by_mnemonic(state, 0x90000178, 24, 3, 1);
1113 status |= update_by_mnemonic(state, 0x9000017C, 0, 3, 1);
1114 status |= update_by_mnemonic(state, 0x9000017C, 4, 3, 1);
1116 status |= update_by_mnemonic(state,
1118 status |= update_by_mnemonic(state,
1120 status |= update_by_mnemonic(state,
1122 status |= update_by_mnemonic(state,
1124 status |= update_by_mnemonic(state,
1126 status |= update_by_mnemonic(state,
1128 status |= update_by_mnemonic(state,
1130 status |= update_by_mnemonic(state,
1132 status |= update_by_mnemonic(state,
1134 status |= update_by_mnemonic(state,
1136 status |= update_by_mnemonic(state,
1138 status |= update_by_mnemonic(state,
1140 status |= update_by_mnemonic(state,
1142 status |= update_by_mnemonic(state,
1144 status |= update_by_mnemonic(state,
1146 status |= update_by_mnemonic(state,
1148 status |= update_by_mnemonic(state,
1150 status |= update_by_mnemonic(state,
1153 status |= update_by_mnemonic(state,
1155 status |= update_by_mnemonic(state,
1157 status |= update_by_mnemonic(state,
1159 status |= update_by_mnemonic(state,
1161 status |= update_by_mnemonic(state,
1163 status |= update_by_mnemonic(state,
1165 status |= update_by_mnemonic(state,
1167 status |= update_by_mnemonic(state,
1169 status |= update_by_mnemonic(state,
1171 status |= update_by_mnemonic(state,
1173 status |= update_by_mnemonic(state,
1175 status |= update_by_mnemonic(state,
1177 status |= update_by_mnemonic(state,
1179 status |= update_by_mnemonic(state,
1181 status |= update_by_mnemonic(state,
1183 status |= update_by_mnemonic(state,
1185 status |= update_by_mnemonic(state,
1187 status |= update_by_mnemonic(state,
1194 status |= update_by_mnemonic(state,
1196 status |= update_by_mnemonic(state,
1198 status |= update_by_mnemonic(state,
1200 status |= update_by_mnemonic(state,
1202 status |= update_by_mnemonic(state,
1204 status |= update_by_mnemonic(state,
1206 status |= update_by_mnemonic(state,
1208 status |= update_by_mnemonic(state,
1210 status |= update_by_mnemonic(state,
1212 status |= update_by_mnemonic(state,
1214 status |= update_by_mnemonic(state,
1216 status |= update_by_mnemonic(state,
1219 status |= update_by_mnemonic(state,
1221 status |= update_by_mnemonic(state,
1223 status |= update_by_mnemonic(state,
1225 status |= update_by_mnemonic(state,
1227 status |= update_by_mnemonic(state,
1229 status |= update_by_mnemonic(state,
1231 status |= update_by_mnemonic(state,
1233 status |= update_by_mnemonic(state,
1235 status |= update_by_mnemonic(state,
1237 status |= update_by_mnemonic(state,
1239 status |= update_by_mnemonic(state,
1242 status |= update_by_mnemonic(state,
1244 status |= update_by_mnemonic(state,
1246 status |= update_by_mnemonic(state,
1248 status |= update_by_mnemonic(state,
1250 status |= update_by_mnemonic(state,
1252 status |= update_by_mnemonic(state,
1254 status |= update_by_mnemonic(state,
1256 status |= update_by_mnemonic(state,
1259 status |= update_by_mnemonic(state,
1261 status |= update_by_mnemonic(state,
1263 status |= update_by_mnemonic(state,
1265 status |= update_by_mnemonic(state,
1267 status |= update_by_mnemonic(state,
1269 status |= update_by_mnemonic(state,
1271 status |= update_by_mnemonic(state,
1273 status |= update_by_mnemonic(state,
1275 status |= update_by_mnemonic(state,
1277 status |= update_by_mnemonic(state,
1279 status |= update_by_mnemonic(state,
1287 status |= update_by_mnemonic(state,
1289 status |= update_by_mnemonic(state,
1291 status |= update_by_mnemonic(state,
1293 status |= update_by_mnemonic(state,
1295 status |= update_by_mnemonic(state,
1297 status |= update_by_mnemonic(state,
1299 status |= update_by_mnemonic(state,
1301 status |= update_by_mnemonic(state,
1303 status |= update_by_mnemonic(state,
1305 status |= update_by_mnemonic(state,
1307 status |= update_by_mnemonic(state,
1314 static int set_drive_strength(struct mxl *state,
1320 read_register(state, 0x90000194, &val);
1321 dev_info(state->i2cdev, "DIGIO = %08x\n", val);
1322 dev_info(state->i2cdev, "set drive_strength = %u\n", ts_drive_strength);
1325 stat |= update_by_mnemonic(state, 0x90000194, 0, 3, ts_drive_strength);
1326 stat |= update_by_mnemonic(state, 0x90000194, 20, 3, ts_drive_strength);
1327 stat |= update_by_mnemonic(state, 0x90000194, 24, 3, ts_drive_strength);
1328 stat |= update_by_mnemonic(state, 0x90000198, 12, 3, ts_drive_strength);
1329 stat |= update_by_mnemonic(state, 0x90000198, 16, 3, ts_drive_strength);
1330 stat |= update_by_mnemonic(state, 0x90000198, 20, 3, ts_drive_strength);
1331 stat |= update_by_mnemonic(state, 0x90000198, 24, 3, ts_drive_strength);
1332 stat |= update_by_mnemonic(state, 0x9000019C, 0, 3, ts_drive_strength);
1333 stat |= update_by_mnemonic(state, 0x9000019C, 4, 3, ts_drive_strength);
1334 stat |= update_by_mnemonic(state, 0x9000019C, 8, 3, ts_drive_strength);
1335 stat |= update_by_mnemonic(state, 0x9000019C, 24, 3, ts_drive_strength);
1336 stat |= update_by_mnemonic(state, 0x9000019C, 28, 3, ts_drive_strength);
1337 stat |= update_by_mnemonic(state, 0x900001A0, 0, 3, ts_drive_strength);
1338 stat |= update_by_mnemonic(state, 0x900001A0, 4, 3, ts_drive_strength);
1339 stat |= update_by_mnemonic(state, 0x900001A0, 20, 3, ts_drive_strength);
1340 stat |= update_by_mnemonic(state, 0x900001A0, 24, 3, ts_drive_strength);
1341 stat |= update_by_mnemonic(state, 0x900001A0, 28, 3, ts_drive_strength);
1346 static int enable_tuner(struct mxl *state, u32 tuner, u32 enable)
1358 stat = send_command(state, cmd_size + MXL_HYDRA_CMD_HEADER_SIZE,
1362 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1365 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1369 read_register(state, HYDRA_TUNER_ENABLE_COMPLETE, &val);
1370 dev_dbg(state->i2cdev, "tuner %u ready = %u\n",
1377 static int config_ts(struct mxl *state, enum MXL_HYDRA_DEMOD_ID_E demod_id,
1440 demod_id = state->base->ts_map[demod_id];
1446 cfg_ts_pad_mux(state, MXL_TRUE);
1447 update_by_mnemonic(state,
1455 if (state->base->chipversion >= 2) {
1456 status |= update_by_mnemonic(state,
1462 update_by_mnemonic(state, 0x90700044, 16, 8, nco_count_min);
1468 status |= update_by_mnemonic(state,
1474 update_by_mnemonic(state, 0x907001D4, 8, 1, clk_type);
1476 status |= update_by_mnemonic(state,
1482 status |= update_by_mnemonic(state,
1488 status |= update_by_mnemonic(state,
1494 status |= update_by_mnemonic(state,
1500 status |= update_by_mnemonic(state,
1506 status |= update_by_mnemonic(state,
1514 status |= update_by_mnemonic(state,
1519 status |= update_by_mnemonic(state,
1527 status |= update_by_mnemonic(state,
1533 status |= update_by_mnemonic(state,
1542 status |= update_by_mnemonic(state,
1548 status |= update_by_mnemonic(state,
1559 status |= update_by_mnemonic(state,
1568 static int config_mux(struct mxl *state)
1570 update_by_mnemonic(state, 0x9070000C, 0, 1, 0);
1571 update_by_mnemonic(state, 0x9070000C, 1, 1, 0);
1572 update_by_mnemonic(state, 0x9070000C, 2, 1, 0);
1573 update_by_mnemonic(state, 0x9070000C, 3, 1, 0);
1574 update_by_mnemonic(state, 0x9070000C, 4, 1, 0);
1575 update_by_mnemonic(state, 0x9070000C, 5, 1, 0);
1576 update_by_mnemonic(state, 0x9070000C, 6, 1, 0);
1577 update_by_mnemonic(state, 0x9070000C, 7, 1, 0);
1578 update_by_mnemonic(state, 0x90700008, 0, 2, 1);
1579 update_by_mnemonic(state, 0x90700008, 2, 2, 1);
1583 static int load_fw(struct mxl *state, struct mxl5xx_cfg *cfg)
1589 return firmware_download(state, cfg->fw, cfg->fw_len);
1599 stat = firmware_download(state, buf, 0x40000);
1605 static int validate_sku(struct mxl *state)
1609 u32 type = state->base->type;
1611 status = read_by_mnemonic(state, 0x90000190, 0, 3, &pad_mux_bond);
1612 status |= read_by_mnemonic(state, 0x80030000, 0, 12, &prcm_chip_id);
1613 status |= read_by_mnemonic(state, 0x80030004, 24, 8, &prcm_so_cid);
1617 dev_info(state->i2cdev, "padMuxBond=%08x, prcmChipId=%08x, prcmSoCId=%08x\n",
1626 state->base->type = MXL_HYDRA_DEVICE_581;
1651 static int get_fwinfo(struct mxl *state)
1656 status = read_by_mnemonic(state, 0x90000190, 0, 3, &val);
1659 dev_info(state->i2cdev, "chipID=%08x\n", val);
1661 status = read_by_mnemonic(state, 0x80030004, 8, 8, &val);
1664 dev_info(state->i2cdev, "chipVer=%08x\n", val);
1666 status = read_register(state, HYDRA_FIRMWARE_VERSION, &val);
1669 dev_info(state->i2cdev, "FWVer=%08x\n", val);
1671 state->base->fwversion = val;
1698 static int probe(struct mxl *state, struct mxl5xx_cfg *cfg)
1704 state->base->ts_map = ts_map1_to_1;
1706 switch (state->base->type) {
1709 state->base->can_clkout = 1;
1710 state->base->demod_num = 8;
1711 state->base->tuner_num = 1;
1712 state->base->sku_type = MXL_HYDRA_SKU_TYPE_581;
1715 state->base->can_clkout = 1;
1716 state->base->demod_num = 8;
1717 state->base->tuner_num = 3;
1718 state->base->sku_type = MXL_HYDRA_SKU_TYPE_582;
1721 state->base->can_clkout = 0;
1722 state->base->demod_num = 8;
1723 state->base->tuner_num = 4;
1724 state->base->sku_type = MXL_HYDRA_SKU_TYPE_585;
1727 state->base->can_clkout = 0;
1728 state->base->demod_num = 4;
1729 state->base->tuner_num = 4;
1730 state->base->sku_type = MXL_HYDRA_SKU_TYPE_544;
1731 state->base->ts_map = ts_map54x;
1735 state->base->can_clkout = 0;
1736 state->base->demod_num = 4;
1737 state->base->tuner_num = 1;
1738 state->base->sku_type = MXL_HYDRA_SKU_TYPE_541;
1739 state->base->ts_map = ts_map54x;
1743 state->base->can_clkout = 0;
1744 state->base->demod_num = 6;
1745 state->base->tuner_num = 1;
1746 state->base->sku_type = MXL_HYDRA_SKU_TYPE_561;
1749 state->base->can_clkout = 0;
1750 state->base->demod_num = 8;
1751 state->base->tuner_num = 1;
1752 state->base->chan_bond = 1;
1753 state->base->sku_type = MXL_HYDRA_SKU_TYPE_568;
1756 state->base->can_clkout = 1;
1757 state->base->demod_num = 4;
1758 state->base->tuner_num = 3;
1759 state->base->sku_type = MXL_HYDRA_SKU_TYPE_542;
1760 state->base->ts_map = ts_map54x;
1765 state->base->can_clkout = 0;
1766 state->base->demod_num = 8;
1767 state->base->tuner_num = 4;
1768 state->base->sku_type = MXL_HYDRA_SKU_TYPE_584;
1772 status = validate_sku(state);
1776 update_by_mnemonic(state, 0x80030014, 9, 1, 1);
1777 update_by_mnemonic(state, 0x8003003C, 12, 1, 1);
1778 status = read_by_mnemonic(state, 0x80030000, 12, 4, &chipver);
1780 state->base->chipversion = 0;
1782 state->base->chipversion = (chipver == 2) ? 2 : 1;
1783 dev_info(state->i2cdev, "Hydra chip version %u\n",
1784 state->base->chipversion);
1786 cfg_dev_xtal(state, cfg->clk, cfg->cap, 0);
1788 fw = firmware_is_alive(state);
1790 status = load_fw(state, cfg);
1794 get_fwinfo(state);
1796 config_mux(state);
1815 for (j = 0; j < state->base->demod_num; j++) {
1816 status = config_ts(state, (enum MXL_HYDRA_DEMOD_ID_E) j,
1821 set_drive_strength(state, 1);
1829 struct mxl *state;
1832 state = kzalloc(sizeof(struct mxl), GFP_KERNEL);
1833 if (!state)
1836 state->demod = demod;
1837 state->tuner = tuner;
1838 state->tuner_in_use = 0xffffffff;
1839 state->i2cdev = &i2c->dev;
1846 state->base = base;
1860 state->base = base;
1861 if (probe(state, cfg) < 0) {
1867 state->fe.ops = mxl_ops;
1868 state->xbar[0] = 4;
1869 state->xbar[1] = demod;
1870 state->xbar[2] = 8;
1871 state->fe.demodulator_priv = state;
1874 list_add(&state->mxl, &base->mxls);
1875 return &state->fe;
1878 kfree(state);