Lines Matching refs:ret
53 int ret;
66 ret = i2c_transfer(state->i2c, msg, 2);
68 if (ret != 2) {
69 printk(KERN_DEBUG "%s: ret == %d\n", __func__, ret);
87 int ret;
113 ret = i2c_transfer(state->i2c, &msg, 1);
115 if (ret != 1) {
116 dprintk("%s: ret == %d\n", __func__, ret);
146 int ret;
149 ret = mt312_readreg(state, VIT_MODE, &vit_mode);
150 if (ret < 0)
151 return ret;
161 int ret;
168 ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h);
169 if (ret < 0)
170 return ret;
174 ret = mt312_writereg(state, MON_CTRL, 0x03);
175 if (ret < 0)
176 return ret;
178 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
179 if (ret < 0)
180 return ret;
187 ret = mt312_writereg(state, MON_CTRL, 0x05);
188 if (ret < 0)
189 return ret;
191 ret = mt312_read(state, MONITOR_H, buf, sizeof(buf));
192 if (ret < 0)
193 return ret;
197 ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf));
198 if (ret < 0)
199 return ret;
219 int ret;
222 ret = mt312_readreg(state, FEC_STATUS, &fec_status);
223 if (ret < 0)
224 return ret;
234 int ret;
238 ret = mt312_writereg(state, CONFIG,
240 if (ret < 0)
241 return ret;
247 ret = mt312_reset(state, 1);
248 if (ret < 0)
249 return ret;
257 ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def));
258 if (ret < 0)
259 return ret;
265 ret = mt312_writereg(state, GPP_CTRL, 0x80);
266 if (ret < 0)
267 return ret;
272 ret = mt312_write(state, HW_CTRL, buf, 2);
273 if (ret < 0)
274 return ret;
277 ret = mt312_writereg(state, HW_CTRL, 0x00);
278 if (ret < 0)
279 return ret;
281 ret = mt312_writereg(state, MPEG_CTRL, 0x00);
282 if (ret < 0)
283 return ret;
294 ret = mt312_write(state, SYS_CLK, buf, sizeof(buf));
295 if (ret < 0)
296 return ret;
298 ret = mt312_writereg(state, SNR_THS_HIGH, 0x32);
299 if (ret < 0)
300 return ret;
312 ret = mt312_writereg(state, OP_CTRL, buf[0]);
313 if (ret < 0)
314 return ret;
320 ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf));
321 if (ret < 0)
322 return ret;
324 ret = mt312_writereg(state, CS_SW_LIM, 0x69);
325 if (ret < 0)
326 return ret;
335 int ret;
341 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
342 if (ret < 0)
343 return ret;
345 ret = mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len);
346 if (ret < 0)
347 return ret;
349 ret = mt312_writereg(state, DISEQC_MODE,
352 if (ret < 0)
353 return ret;
360 ret = mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40));
361 if (ret < 0)
362 return ret;
374 int ret;
380 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
381 if (ret < 0)
382 return ret;
384 ret = mt312_writereg(state, DISEQC_MODE,
386 if (ret < 0)
387 return ret;
398 int ret;
404 ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode);
405 if (ret < 0)
406 return ret;
408 ret = mt312_writereg(state, DISEQC_MODE,
410 if (ret < 0)
411 return ret;
436 int ret;
441 ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status));
442 if (ret < 0)
443 return ret;
465 int ret;
468 ret = mt312_read(state, RS_BERCNT_H, buf, 3);
469 if (ret < 0)
470 return ret;
481 int ret;
486 ret = mt312_read(state, AGC_H, buf, sizeof(buf));
487 if (ret < 0)
488 return ret;
503 int ret;
506 ret = mt312_read(state, M_SNR_H, buf, sizeof(buf));
507 if (ret < 0)
508 return ret;
518 int ret;
521 ret = mt312_read(state, RS_UBC_H, buf, sizeof(buf));
522 if (ret < 0)
523 return ret;
534 int ret;
570 ret = mt312_readreg(state, CONFIG, &config_val);
571 if (ret < 0)
572 return ret;
578 ret = mt312_initfe(fe);
579 if (ret < 0)
580 return ret;
586 ret = mt312_initfe(fe);
587 if (ret < 0)
588 return ret;
626 ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf));
627 if (ret < 0)
628 return ret;
630 ret = mt312_reset(state, 0);
631 if (ret < 0)
632 return ret;
641 int ret;
643 ret = mt312_get_inversion(state, &p->inversion);
644 if (ret < 0)
645 return ret;
647 ret = mt312_get_symbol_rate(state, &p->symbol_rate);
648 if (ret < 0)
649 return ret;
651 ret = mt312_get_code_rate(state, &p->fec_inner);
652 if (ret < 0)
653 return ret;
663 int ret;
667 ret = mt312_readreg(state, GPP_CTRL, &val);
668 if (ret < 0)
681 ret = mt312_writereg(state, GPP_CTRL, val);
684 return ret;
690 int ret;
694 ret = mt312_reset(state, 1);
695 if (ret < 0)
696 return ret;
700 ret = mt312_writereg(state, GPP_CTRL, 0x00);
701 if (ret < 0)
702 return ret;
705 ret = mt312_writereg(state, HW_CTRL, 0x0d);
706 if (ret < 0)
707 return ret;
710 ret = mt312_readreg(state, CONFIG, &config);
711 if (ret < 0)
712 return ret;
715 ret = mt312_writereg(state, CONFIG, config & 0x7f);
716 if (ret < 0)
717 return ret;