Lines Matching refs:target_mclk
628 u32 tuner_frequency_khz, target_mclk, u32tmp;
698 target_mclk = 96000000;
700 target_mclk = 144000000;
704 m88ds3103b_set_mclk(dev, target_mclk / 1000);
719 target_mclk = dev->cfg->ts_clk;
724 target_mclk = 96000000;
727 target_mclk = 96000000;
729 target_mclk = 144000000;
731 target_mclk = 192000000;
740 switch (target_mclk) {
907 u16tmp = DIV_ROUND_UP(target_mclk, dev->cfg->ts_clk);
912 dev_dbg(&client->dev, "target_mclk=%u ts_clk=%u ts_clk_divide_ratio=%u\n",
913 target_mclk, dev->cfg->ts_clk, u16tmp);
934 m88ds3103b_set_mclk(dev, target_mclk / 1000);