Lines Matching refs:ret
54 #define lg_chkerr(ret) \
57 __ret = (ret < 0); \
59 pr_err("error %d on line %d\n", ret, __LINE__); \
125 int ret;
134 ret = i2c_transfer(state->i2c_adap, &msg, 1);
136 if (ret != 1) {
138 msg.buf[0], msg.buf[1], msg.buf[2], ret);
139 if (ret < 0)
140 return ret;
149 int ret;
158 ret = i2c_transfer(state->i2c_adap, msg, 2);
160 if (ret != 2) {
161 pr_err("error (addr %02x reg %04x error (ret == %i)\n",
162 state->cfg->i2c_addr, reg, ret);
163 if (ret < 0)
164 return ret;
176 int ret = lgdt3306a_read_reg(state, reg, &__val); \
177 if (lg_chkerr(ret)) \
186 int ret;
190 ret = lgdt3306a_read_reg(state, reg, &val);
191 if (lg_chkerr(ret))
197 ret = lgdt3306a_write_reg(state, reg, val);
198 lg_chkerr(ret);
200 return ret;
207 int ret;
211 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
212 if (lg_chkerr(ret))
216 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
217 lg_chkerr(ret);
220 return ret;
227 int ret;
231 ret = lgdt3306a_set_reg_bit(state, 0x0071, 7,
233 if (lg_chkerr(ret))
240 ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0);
241 if (lg_chkerr(ret))
244 ret = lgdt3306a_read_reg(state, 0x0070, &val);
245 if (lg_chkerr(ret))
253 ret = lgdt3306a_write_reg(state, 0x0070, val);
254 lg_chkerr(ret);
257 return ret;
265 int ret;
269 ret = lgdt3306a_read_reg(state, 0x0070, &val);
270 if (lg_chkerr(ret))
280 ret = lgdt3306a_write_reg(state, 0x0070, val);
281 lg_chkerr(ret);
284 return ret;
291 int ret;
296 ret = lgdt3306a_read_reg(state, 0x0070, &val);
297 if (lg_chkerr(ret))
304 ret = lgdt3306a_write_reg(state, 0x0070, val);
305 if (lg_chkerr(ret))
309 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1);
310 if (lg_chkerr(ret))
315 ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0);
316 if (lg_chkerr(ret))
319 ret = lgdt3306a_read_reg(state, 0x0070, &val);
320 if (lg_chkerr(ret))
324 ret = lgdt3306a_write_reg(state, 0x0070, val);
325 if (lg_chkerr(ret))
330 return ret;
346 int ret;
352 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
353 if (lg_chkerr(ret))
357 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0);
358 if (lg_chkerr(ret))
363 ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
364 if (lg_chkerr(ret))
368 ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1);
369 if (lg_chkerr(ret))
377 return ret;
384 int ret;
389 ret = lgdt3306a_read_reg(state, 0x0002, &val);
392 ret = lgdt3306a_write_reg(state, 0x0002, val);
393 if (lg_chkerr(ret))
397 ret = lgdt3306a_write_reg(state, 0x0008, 0x80);
398 if (lg_chkerr(ret))
402 ret = lgdt3306a_read_reg(state, 0x0009, &val);
405 ret = lgdt3306a_write_reg(state, 0x0009, val);
406 if (lg_chkerr(ret))
410 ret = lgdt3306a_read_reg(state, 0x0009, &val);
412 ret = lgdt3306a_write_reg(state, 0x0009, val);
413 if (lg_chkerr(ret))
417 ret = lgdt3306a_read_reg(state, 0x000d, &val);
419 ret = lgdt3306a_write_reg(state, 0x000d, val);
420 if (lg_chkerr(ret))
426 ret = lgdt3306a_write_reg(state, 0x0024, 0x00);
427 if (lg_chkerr(ret))
431 ret = lgdt3306a_write_reg(state, 0x002e, 0x00);
432 ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
433 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
436 ret = lgdt3306a_write_reg(state, 0x002b, 0x00);
437 ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
438 ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
441 ret = lgdt3306a_write_reg(state, 0x0028, 0x00);
442 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
443 ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
446 ret = lgdt3306a_write_reg(state, 0x0025, 0x00);
447 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
448 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
454 ret = lgdt3306a_write_reg(state, 0x0024, 0x5A);
455 if (lg_chkerr(ret))
459 ret = lgdt3306a_write_reg(state, 0x002e, 0x5A);
460 ret = lgdt3306a_write_reg(state, 0x002f, 0x00);
461 ret = lgdt3306a_write_reg(state, 0x0030, 0x00);
464 ret = lgdt3306a_write_reg(state, 0x002b, 0x36);
465 ret = lgdt3306a_write_reg(state, 0x002c, 0x00);
466 ret = lgdt3306a_write_reg(state, 0x002d, 0x00);
469 ret = lgdt3306a_write_reg(state, 0x0028, 0x2A);
470 ret = lgdt3306a_write_reg(state, 0x0029, 0x00);
471 ret = lgdt3306a_write_reg(state, 0x002a, 0x00);
474 ret = lgdt3306a_write_reg(state, 0x0025, 0x06);
475 ret = lgdt3306a_write_reg(state, 0x0026, 0x00);
476 ret = lgdt3306a_write_reg(state, 0x0027, 0x00);
479 ret = lgdt3306a_read_reg(state, 0x001e, &val);
482 ret = lgdt3306a_write_reg(state, 0x001e, val);
484 ret = lgdt3306a_write_reg(state, 0x0022, 0x08);
486 ret = lgdt3306a_write_reg(state, 0x0023, 0xFF);
488 ret = lgdt3306a_read_reg(state, 0x211f, &val);
490 ret = lgdt3306a_write_reg(state, 0x211f, val);
492 ret = lgdt3306a_write_reg(state, 0x2173, 0x01);
494 ret = lgdt3306a_read_reg(state, 0x1061, &val);
497 ret = lgdt3306a_write_reg(state, 0x1061, val);
499 ret = lgdt3306a_read_reg(state, 0x103d, &val);
501 ret = lgdt3306a_write_reg(state, 0x103d, val);
503 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
505 ret = lgdt3306a_read_reg(state, 0x2141, &val);
507 ret = lgdt3306a_write_reg(state, 0x2141, val);
509 ret = lgdt3306a_read_reg(state, 0x2135, &val);
512 ret = lgdt3306a_write_reg(state, 0x2135, val);
514 ret = lgdt3306a_read_reg(state, 0x0003, &val);
516 ret = lgdt3306a_write_reg(state, 0x0003, val);
518 ret = lgdt3306a_read_reg(state, 0x001c, &val);
520 ret = lgdt3306a_write_reg(state, 0x001c, val);
523 ret = lgdt3306a_read_reg(state, 0x2179, &val);
525 ret = lgdt3306a_write_reg(state, 0x2179, val);
527 ret = lgdt3306a_read_reg(state, 0x217a, &val);
529 ret = lgdt3306a_write_reg(state, 0x217a, val);
532 ret = lgdt3306a_soft_reset(state);
533 if (lg_chkerr(ret))
538 return ret;
544 int ret;
549 ret = lgdt3306a_write_reg(state, 0x0008, 0x08);
550 if (lg_chkerr(ret))
554 ret = lgdt3306a_read_reg(state, 0x0002, &val);
557 ret = lgdt3306a_write_reg(state, 0x0002, val);
558 if (lg_chkerr(ret))
562 ret = lgdt3306a_read_reg(state, 0x0009, &val);
564 ret = lgdt3306a_write_reg(state, 0x0009, val);
565 if (lg_chkerr(ret))
569 ret = lgdt3306a_read_reg(state, 0x0009, &val);
577 ret = lgdt3306a_write_reg(state, 0x0009, val);
578 if (lg_chkerr(ret))
582 ret = lgdt3306a_read_reg(state, 0x101a, &val);
589 ret = lgdt3306a_write_reg(state, 0x101a, val);
590 if (lg_chkerr(ret))
594 ret = lgdt3306a_read_reg(state, 0x000d, &val);
597 ret = lgdt3306a_write_reg(state, 0x000d, val);
598 if (lg_chkerr(ret))
602 ret = lgdt3306a_read_reg(state, 0x0024, &val);
604 ret = lgdt3306a_write_reg(state, 0x0024, val);
605 if (lg_chkerr(ret))
609 ret = lgdt3306a_read_reg(state, 0x000a, &val);
612 ret = lgdt3306a_write_reg(state, 0x000a, val);
613 if (lg_chkerr(ret))
617 ret = lgdt3306a_read_reg(state, 0x2849, &val);
619 ret = lgdt3306a_write_reg(state, 0x2849, val);
620 if (lg_chkerr(ret))
624 ret = lgdt3306a_read_reg(state, 0x302b, &val);
626 ret = lgdt3306a_write_reg(state, 0x302b, val);
627 if (lg_chkerr(ret))
631 ret = lgdt3306a_soft_reset(state);
632 if (lg_chkerr(ret))
637 return ret;
643 int ret;
649 ret = lgdt3306a_set_vsb(state);
654 ret = lgdt3306a_set_qam(state, p->modulation);
659 if (lg_chkerr(ret))
665 return ret;
694 int ret;
698 ret = lgdt3306a_set_reg_bit(state, 0x0002, 2, inversion ? 1 : 0);
699 return ret;
705 int ret;
710 ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);
711 return ret;
717 int ret;
760 ret = lgdt3306a_write_reg(state, 0x0010, nco1);
761 if (ret)
762 return ret;
763 ret = lgdt3306a_write_reg(state, 0x0011, nco2);
764 if (ret)
765 return ret;
790 int ret;
795 ret = lgdt3306a_mpeg_tristate(state, 1); /* disable data bus */
796 if (lg_chkerr(ret))
799 ret = lgdt3306a_power(state, 0); /* power down */
800 lg_chkerr(ret);
818 int ret;
823 ret = lgdt3306a_set_reg_bit(state, 0x0001, 0, 1); /* SIMFASTENB=0x01 */
824 if (lg_chkerr(ret))
828 ret = lgdt3306a_set_inversion_auto(state, 0);
829 if (lg_chkerr(ret))
833 ret = lgdt3306a_set_inversion(state, 1);
834 if (lg_chkerr(ret))
840 ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1);
841 if (lg_chkerr(ret))
847 ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0);
848 if (lg_chkerr(ret))
854 ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0);
855 if (lg_chkerr(ret))
861 ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0);
862 if (lg_chkerr(ret))
867 ret = lgdt3306a_read_reg(state, 0x0005, &val);
868 if (lg_chkerr(ret))
872 ret = lgdt3306a_write_reg(state, 0x0005, val);
873 if (lg_chkerr(ret))
875 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
876 if (lg_chkerr(ret))
880 ret = lgdt3306a_read_reg(state, 0x000d, &val);
881 if (lg_chkerr(ret))
885 ret = lgdt3306a_write_reg(state, 0x000d, val);
886 if (lg_chkerr(ret))
891 ret = lgdt3306a_read_reg(state, 0x0005, &val);
892 if (lg_chkerr(ret))
896 ret = lgdt3306a_write_reg(state, 0x0005, val);
897 if (lg_chkerr(ret))
899 ret = lgdt3306a_write_reg(state, 0x0006, 0x64);
900 if (lg_chkerr(ret))
904 ret = lgdt3306a_read_reg(state, 0x000d, &val);
905 if (lg_chkerr(ret))
909 ret = lgdt3306a_write_reg(state, 0x000d, val);
910 if (lg_chkerr(ret))
916 ret = lgdt3306a_write_reg(state, 0x000e, 0x00);
917 ret = lgdt3306a_write_reg(state, 0x000f, 0x00);
921 ret = lgdt3306a_write_reg(state, 0x0010, 0x34); /* 3.25MHz */
922 ret = lgdt3306a_write_reg(state, 0x0011, 0x00);
925 ret = lgdt3306a_write_reg(state, 0x0014, 0); /* gain error=0 */
928 ret = lgdt3306a_read_reg(state, 0x103c, &val);
931 ret = lgdt3306a_write_reg(state, 0x103c, val);
934 ret = lgdt3306a_read_reg(state, 0x103d, &val);
937 ret = lgdt3306a_write_reg(state, 0x103d, val);
940 ret = lgdt3306a_read_reg(state, 0x1036, &val);
943 ret = lgdt3306a_write_reg(state, 0x1036, val);
946 ret = lgdt3306a_read_reg(state, 0x211f, &val);
948 ret = lgdt3306a_write_reg(state, 0x211f, val);
951 ret = lgdt3306a_read_reg(state, 0x2849, &val);
953 ret = lgdt3306a_write_reg(state, 0x2849, val);
956 ret = lgdt3306a_set_vsb(state);
959 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
962 ret = lgdt3306a_mpeg_tristate(state, 1);
965 ret = lgdt3306a_sleep(state);
966 lg_chkerr(ret);
972 return ret;
979 int ret;
991 ret = lgdt3306a_power(state, 1); /* power up */
992 if (lg_chkerr(ret))
996 ret = fe->ops.tuner_ops.set_params(fe);
1000 if (lg_chkerr(ret))
1006 ret = lgdt3306a_set_modulation(state, p);
1007 if (lg_chkerr(ret))
1010 ret = lgdt3306a_agc_setup(state, p);
1011 if (lg_chkerr(ret))
1014 ret = lgdt3306a_set_if(state, p);
1015 if (lg_chkerr(ret))
1020 ret = lgdt3306a_mpeg_mode(state, state->cfg->mpeg_mode);
1021 if (lg_chkerr(ret))
1024 ret = lgdt3306a_mpeg_mode_polarity(state,
1027 if (lg_chkerr(ret))
1030 ret = lgdt3306a_mpeg_tristate(state, 0); /* enable data bus */
1031 if (lg_chkerr(ret))
1034 ret = lgdt3306a_soft_reset(state);
1035 if (lg_chkerr(ret))
1043 return ret;
1072 int ret;
1076 ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1077 if (ret)
1078 return ret;
1081 ret = lgdt3306a_read_reg(state, 0x2185, &maxPowerMan);
1082 if (ret)
1083 return ret;
1085 ret = lgdt3306a_read_reg(state, 0x2191, &val);
1086 if (ret)
1087 return ret;
1090 ret = lgdt3306a_read_reg(state, 0x2180, &val);
1091 if (ret)
1092 return ret;
1095 ret = lgdt3306a_read_reg(state, 0x2181, &val);
1096 if (ret)
1097 return ret;
1104 ret = lgdt3306a_read_reg(state, 0x1061, &val);
1105 if (ret)
1106 return ret;
1116 ret = lgdt3306a_write_reg(state, 0x1061, val);
1117 if (ret)
1118 return ret;
1121 ret = lgdt3306a_read_reg(state, 0x0024, &val);
1122 if (ret)
1123 return ret;
1128 ret = lgdt3306a_write_reg(state, 0x0024, val);
1129 if (ret)
1130 return ret;
1133 ret = lgdt3306a_read_reg(state, 0x103d, &val);
1134 if (ret)
1135 return ret;
1138 ret = lgdt3306a_write_reg(state, 0x103d, val);
1140 return ret;
1147 int ret;
1149 ret = lgdt3306a_read_reg(state, 0x0081, &val);
1150 if (ret)
1158 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1159 if (ret)
1179 int ret;
1188 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1189 if (ret)
1190 return ret;
1202 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1203 if (ret)
1204 return ret;
1218 ret = lgdt3306a_read_reg(state, 0x1094, &val);
1219 if (ret)
1220 return ret;
1236 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1237 if (ret)
1238 return ret;
1264 int ret;
1267 ret = lgdt3306a_read_reg(state, 0x0080, &val);
1268 if (ret)
1269 return ret;
1280 int ret;
1284 ret = lgdt3306a_read_reg(state, 0x21bc, &currChDiffACQ);
1285 if (ret)
1286 return ret;
1289 ret = lgdt3306a_read_reg(state, 0x21a1, &val);
1290 if (ret)
1291 return ret;
1295 ret = lgdt3306a_read_reg(state, 0x2199, &val);
1296 if (ret)
1297 return ret;
1300 ret = lgdt3306a_read_reg(state, 0x0090, &val);
1301 if (ret)
1302 return ret;
1313 ret = lgdt3306a_read_reg(state, 0x2135, &val);
1314 if (ret)
1315 return ret;
1318 ret = lgdt3306a_write_reg(state, 0x2135, val);
1319 if (ret)
1320 return ret;
1322 ret = lgdt3306a_read_reg(state, 0x2141, &val);
1323 if (ret)
1324 return ret;
1327 ret = lgdt3306a_write_reg(state, 0x2141, val);
1328 if (ret)
1329 return ret;
1331 ret = lgdt3306a_write_reg(state, 0x2122, 0x70);
1332 if (ret)
1333 return ret;
1335 ret = lgdt3306a_read_reg(state, 0x2135, &val);
1336 if (ret)
1337 return ret;
1340 ret = lgdt3306a_write_reg(state, 0x2135, val);
1341 if (ret)
1342 return ret;
1344 ret = lgdt3306a_read_reg(state, 0x2141, &val);
1345 if (ret)
1346 return ret;
1349 ret = lgdt3306a_write_reg(state, 0x2141, val);
1350 if (ret)
1351 return ret;
1353 ret = lgdt3306a_write_reg(state, 0x2122, 0x40);
1354 if (ret)
1355 return ret;
1425 int ret;
1427 ret = lgdt3306a_read_reg(state, 0x00fa, &val);
1428 if (ret)
1429 return ret;
1509 int ret;
1521 ret = lgdt3306a_pre_monitoring(state);
1522 if (ret)
1570 int ret = 0;
1573 ret = fe->ops.tuner_ops.get_rf_strength(fe, &strength);
1574 if (ret == 0)
1603 ret = lgdt3306a_monitor_vsb(state);
1607 ret = -EINVAL;
1619 return ret;
1643 int ret;
1657 ret = lgdt3306a_read_reg(state, 0x00a6, &val);
1658 if (lg_chkerr(ret))
1670 ret = fe->ops.read_snr(fe, &snr);
1671 if (lg_chkerr(ret))
1690 return ret;
1733 int ret = 0;
1740 ret = lgdt3306a_set_parameters(fe);
1741 if (ret != 0)
1742 return ret;
1745 ret = lgdt3306a_read_status(fe, status);
1747 return ret;
1762 int ret;
1765 ret = lgdt3306a_set_parameters(fe);
1766 if (ret)
1769 ret = lgdt3306a_read_status(fe, &status);
1770 if (ret)
1780 dbg_info("failed (%d)\n", ret);
1798 int ret;
1819 ret = lgdt3306a_read_reg(state, 0x0000, &val);
1820 if (lg_chkerr(ret))
1829 ret = lgdt3306a_read_reg(state, 0x0001, &val);
1830 if (lg_chkerr(ret))
1839 ret = lgdt3306a_read_reg(state, 0x0002, &val);
1840 if (lg_chkerr(ret))
2177 int ret;
2182 ret = -ENOMEM;
2189 ret = -ENODEV;
2202 ret = -ENOMEM;
2206 ret = i2c_mux_add_adapter(state->muxc, 0, 0, 0);
2207 if (ret)
2224 dev_warn(&client->dev, "probe failed = %d\n", ret);
2225 return ret;