Lines Matching refs:state
25 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode);
26 static int power_down_qam(struct drxk_state *state);
27 static int set_dvbt_standard(struct drxk_state *state,
29 static int set_qam_standard(struct drxk_state *state,
31 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
33 static int set_dvbt_standard(struct drxk_state *state,
35 static int dvbt_start(struct drxk_state *state);
36 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
38 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status);
39 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status);
40 static int switch_antenna_to_qam(struct drxk_state *state);
41 static int switch_antenna_to_dvbt(struct drxk_state *state);
43 static bool is_dvbt(struct drxk_state *state)
45 return state->m_operation_mode == OM_DVBT;
48 static bool is_qam(struct drxk_state *state)
50 return state->m_operation_mode == OM_QAM_ITU_A ||
51 state->m_operation_mode == OM_QAM_ITU_B ||
52 state->m_operation_mode == OM_QAM_ITU_C;
94 #define DRXK_KI_RAGC_DVBT (IsA1WithPatchCode(state) ? 3 : 2)
97 #define DRXK_KI_IAGC_DVBT (IsA1WithPatchCode(state) ? 4 : 2)
100 #define DRXK_KI_DAGC_DVBT (IsA1WithPatchCode(state) ? 10 : 7)
191 static int drxk_i2c_lock(struct drxk_state *state)
193 i2c_lock_bus(state->i2c, I2C_LOCK_SEGMENT);
194 state->drxk_i2c_exclusive_lock = true;
199 static void drxk_i2c_unlock(struct drxk_state *state)
201 if (!state->drxk_i2c_exclusive_lock)
204 i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT);
205 state->drxk_i2c_exclusive_lock = false;
208 static int drxk_i2c_transfer(struct drxk_state *state, struct i2c_msg *msgs,
211 if (state->drxk_i2c_exclusive_lock)
212 return __i2c_transfer(state->i2c, msgs, len);
214 return i2c_transfer(state->i2c, msgs, len);
217 static int i2c_read1(struct drxk_state *state, u8 adr, u8 *val)
223 return drxk_i2c_transfer(state, msgs, 1);
226 static int i2c_write(struct drxk_state *state, u8 adr, u8 *data, int len)
234 status = drxk_i2c_transfer(state, &msg, 1);
244 static int i2c_read(struct drxk_state *state,
255 status = drxk_i2c_transfer(state, msgs, 2);
269 static int read16_flags(struct drxk_state *state, u32 reg, u16 *data, u8 flags)
272 u8 adr = state->demod_address, mm1[4], mm2[2], len;
274 if (state->single_master)
289 status = i2c_read(state, adr, mm1, len, mm2, 2);
298 static int read16(struct drxk_state *state, u32 reg, u16 *data)
300 return read16_flags(state, reg, data, 0);
303 static int read32_flags(struct drxk_state *state, u32 reg, u32 *data, u8 flags)
306 u8 adr = state->demod_address, mm1[4], mm2[4], len;
308 if (state->single_master)
323 status = i2c_read(state, adr, mm1, len, mm2, 4);
333 static int read32(struct drxk_state *state, u32 reg, u32 *data)
335 return read32_flags(state, reg, data, 0);
338 static int write16_flags(struct drxk_state *state, u32 reg, u16 data, u8 flags)
340 u8 adr = state->demod_address, mm[6], len;
342 if (state->single_master)
359 return i2c_write(state, adr, mm, len + 2);
362 static int write16(struct drxk_state *state, u32 reg, u16 data)
364 return write16_flags(state, reg, data, 0);
367 static int write32_flags(struct drxk_state *state, u32 reg, u32 data, u8 flags)
369 u8 adr = state->demod_address, mm[8], len;
371 if (state->single_master)
390 return i2c_write(state, adr, mm, len + 4);
393 static int write32(struct drxk_state *state, u32 reg, u32 data)
395 return write32_flags(state, reg, data, 0);
398 static int write_block(struct drxk_state *state, u32 address,
404 if (state->single_master)
408 int chunk = blk_size > state->m_chunk_size ?
409 state->m_chunk_size : blk_size;
410 u8 *adr_buf = &state->chunk[0];
420 if (chunk == state->m_chunk_size)
428 memcpy(&state->chunk[adr_length], p_block, chunk);
432 status = i2c_write(state, state->demod_address,
433 &state->chunk[0], chunk + adr_length);
450 static int power_up_device(struct drxk_state *state)
458 status = i2c_read1(state, state->demod_address, &data);
462 status = i2c_write(state, state->demod_address,
468 status = i2c_read1(state, state->demod_address,
477 status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_NONE);
480 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
484 status = write16(state, SIO_CC_PLL_LOCK__A, 1);
488 state->m_current_power_mode = DRX_POWER_UP;
498 static int init_state(struct drxk_state *state)
554 state->m_has_lna = false;
555 state->m_has_dvbt = false;
556 state->m_has_dvbc = false;
557 state->m_has_atv = false;
558 state->m_has_oob = false;
559 state->m_has_audio = false;
561 if (!state->m_chunk_size)
562 state->m_chunk_size = 124;
564 state->m_osc_clock_freq = 0;
565 state->m_smart_ant_inverted = false;
566 state->m_b_p_down_open_bridge = false;
569 state->m_sys_clock_freq = 151875;
572 state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) *
575 if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M)
576 state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M;
577 state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
579 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
581 state->m_b_power_down = (ul_power_down != 0);
583 state->m_drxk_a3_patch_code = false;
587 state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode;
588 state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level;
589 state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level;
590 state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level;
591 state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed;
592 state->m_vsb_pga_cfg = 140;
595 state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode;
596 state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level;
597 state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level;
598 state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level;
599 state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed;
600 state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top;
601 state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current;
602 state->m_vsb_pre_saw_cfg.reference = 0x07;
603 state->m_vsb_pre_saw_cfg.use_pre_saw = true;
605 state->m_Quality83percent = DEFAULT_MER_83;
606 state->m_Quality93percent = DEFAULT_MER_93;
608 state->m_Quality83percent = ulQual83;
609 state->m_Quality93percent = ulQual93;
613 state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode;
614 state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level;
615 state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level;
616 state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level;
617 state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed;
620 state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode;
621 state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level;
622 state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level;
623 state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level;
624 state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed;
625 state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top;
626 state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current;
627 state->m_atv_pre_saw_cfg.reference = 0x04;
628 state->m_atv_pre_saw_cfg.use_pre_saw = true;
632 state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
633 state->m_dvbt_rf_agc_cfg.output_level = 0;
634 state->m_dvbt_rf_agc_cfg.min_output_level = 0;
635 state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF;
636 state->m_dvbt_rf_agc_cfg.top = 0x2100;
637 state->m_dvbt_rf_agc_cfg.cut_off_current = 4000;
638 state->m_dvbt_rf_agc_cfg.speed = 1;
642 state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
643 state->m_dvbt_if_agc_cfg.output_level = 0;
644 state->m_dvbt_if_agc_cfg.min_output_level = 0;
645 state->m_dvbt_if_agc_cfg.max_output_level = 9000;
646 state->m_dvbt_if_agc_cfg.top = 13424;
647 state->m_dvbt_if_agc_cfg.cut_off_current = 0;
648 state->m_dvbt_if_agc_cfg.speed = 3;
649 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30;
650 state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000;
651 /* state->m_dvbtPgaCfg = 140; */
653 state->m_dvbt_pre_saw_cfg.reference = 4;
654 state->m_dvbt_pre_saw_cfg.use_pre_saw = false;
657 state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF;
658 state->m_qam_rf_agc_cfg.output_level = 0;
659 state->m_qam_rf_agc_cfg.min_output_level = 6023;
660 state->m_qam_rf_agc_cfg.max_output_level = 27000;
661 state->m_qam_rf_agc_cfg.top = 0x2380;
662 state->m_qam_rf_agc_cfg.cut_off_current = 4000;
663 state->m_qam_rf_agc_cfg.speed = 3;
666 state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO;
667 state->m_qam_if_agc_cfg.output_level = 0;
668 state->m_qam_if_agc_cfg.min_output_level = 0;
669 state->m_qam_if_agc_cfg.max_output_level = 9000;
670 state->m_qam_if_agc_cfg.top = 0x0511;
671 state->m_qam_if_agc_cfg.cut_off_current = 0;
672 state->m_qam_if_agc_cfg.speed = 3;
673 state->m_qam_if_agc_cfg.ingain_tgt_max = 5119;
674 state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50;
676 state->m_qam_pga_cfg = 140;
677 state->m_qam_pre_saw_cfg.reference = 4;
678 state->m_qam_pre_saw_cfg.use_pre_saw = false;
680 state->m_operation_mode = OM_NONE;
681 state->m_drxk_state = DRXK_UNINITIALIZED;
684 state->m_enable_mpeg_output = true; /* If TRUE; enable MPEG output */
685 state->m_insert_rs_byte = false; /* If TRUE; insert RS byte */
686 state->m_invert_data = false; /* If TRUE; invert DATA signals */
687 state->m_invert_err = false; /* If TRUE; invert ERR signal */
688 state->m_invert_str = false; /* If TRUE; invert STR signals */
689 state->m_invert_val = false; /* If TRUE; invert VAL signals */
690 state->m_invert_clk = (ul_invert_ts_clock != 0); /* If TRUE; invert CLK signals */
695 state->m_dvbt_bitrate = ul_dvbt_bitrate;
696 state->m_dvbc_bitrate = ul_dvbc_bitrate;
698 state->m_ts_data_strength = (ul_ts_data_strength & 0x07);
701 state->m_mpeg_ts_static_bitrate = 19392658;
702 state->m_disable_te_ihandling = false;
705 state->m_insert_rs_byte = true;
707 state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT;
709 state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out;
710 state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT;
712 state->m_demod_lock_time_out = ul_demod_lock_time_out;
715 state->m_constellation = DRX_CONSTELLATION_AUTO;
716 state->m_qam_interleave_mode = DRXK_QAM_I12_J17;
717 state->m_fec_rs_plen = 204 * 8; /* fecRsPlen annex A */
718 state->m_fec_rs_prescale = 1;
720 state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM;
721 state->m_agcfast_clip_ctrl_delay = 0;
723 state->m_gpio_cfg = ul_gpio_cfg;
725 state->m_b_power_down = false;
726 state->m_current_power_mode = DRX_POWER_DOWN;
728 state->m_rfmirror = (ul_rf_mirror == 0);
729 state->m_if_agc_pol = false;
733 static int drxx_open(struct drxk_state *state)
742 status = write16(state, SCU_RAM_GPIO__A,
747 status = read16(state, SIO_TOP_COMM_KEY__A, &key);
750 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
753 status = read32(state, SIO_TOP_JTAGID_LO__A, &jtag);
756 status = read16(state, SIO_PDR_UIO_IN_HI__A, &bid);
759 status = write16(state, SIO_TOP_COMM_KEY__A, key);
766 static int get_device_capabilities(struct drxk_state *state)
777 status = write16(state, SCU_RAM_GPIO__A,
781 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
784 status = read16(state, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg);
787 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
797 state->m_osc_clock_freq = 27000;
801 state->m_osc_clock_freq = 20250;
805 state->m_osc_clock_freq = 20250;
815 status = read32(state, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo);
824 state->m_device_spin = DRXK_SPIN_A1;
828 state->m_device_spin = DRXK_SPIN_A2;
832 state->m_device_spin = DRXK_SPIN_A3;
836 state->m_device_spin = DRXK_SPIN_UNKNOWN;
844 state->m_has_lna = false;
845 state->m_has_oob = false;
846 state->m_has_atv = false;
847 state->m_has_audio = false;
848 state->m_has_dvbt = true;
849 state->m_has_dvbc = true;
850 state->m_has_sawsw = true;
851 state->m_has_gpio2 = false;
852 state->m_has_gpio1 = false;
853 state->m_has_irqn = false;
857 state->m_has_lna = false;
858 state->m_has_oob = false;
859 state->m_has_atv = true;
860 state->m_has_audio = false;
861 state->m_has_dvbt = true;
862 state->m_has_dvbc = false;
863 state->m_has_sawsw = true;
864 state->m_has_gpio2 = true;
865 state->m_has_gpio1 = true;
866 state->m_has_irqn = false;
870 state->m_has_lna = false;
871 state->m_has_oob = false;
872 state->m_has_atv = true;
873 state->m_has_audio = false;
874 state->m_has_dvbt = true;
875 state->m_has_dvbc = false;
876 state->m_has_sawsw = true;
877 state->m_has_gpio2 = true;
878 state->m_has_gpio1 = true;
879 state->m_has_irqn = false;
883 state->m_has_lna = false;
884 state->m_has_oob = false;
885 state->m_has_atv = true;
886 state->m_has_audio = true;
887 state->m_has_dvbt = true;
888 state->m_has_dvbc = false;
889 state->m_has_sawsw = true;
890 state->m_has_gpio2 = true;
891 state->m_has_gpio1 = true;
892 state->m_has_irqn = false;
896 state->m_has_lna = false;
897 state->m_has_oob = false;
898 state->m_has_atv = true;
899 state->m_has_audio = true;
900 state->m_has_dvbt = true;
901 state->m_has_dvbc = true;
902 state->m_has_sawsw = true;
903 state->m_has_gpio2 = true;
904 state->m_has_gpio1 = true;
905 state->m_has_irqn = false;
909 state->m_has_lna = false;
910 state->m_has_oob = false;
911 state->m_has_atv = true;
912 state->m_has_audio = true;
913 state->m_has_dvbt = true;
914 state->m_has_dvbc = true;
915 state->m_has_sawsw = true;
916 state->m_has_gpio2 = true;
917 state->m_has_gpio1 = true;
918 state->m_has_irqn = false;
922 state->m_has_lna = false;
923 state->m_has_oob = false;
924 state->m_has_atv = true;
925 state->m_has_audio = true;
926 state->m_has_dvbt = true;
927 state->m_has_dvbc = true;
928 state->m_has_sawsw = true;
929 state->m_has_gpio2 = true;
930 state->m_has_gpio1 = true;
931 state->m_has_irqn = false;
935 state->m_has_lna = false;
936 state->m_has_oob = false;
937 state->m_has_atv = true;
938 state->m_has_audio = false;
939 state->m_has_dvbt = true;
940 state->m_has_dvbc = true;
941 state->m_has_sawsw = true;
942 state->m_has_gpio2 = true;
943 state->m_has_gpio1 = true;
944 state->m_has_irqn = false;
955 state->m_osc_clock_freq / 1000,
956 state->m_osc_clock_freq % 1000);
966 static int hi_command(struct drxk_state *state, u16 cmd, u16 *p_result)
974 status = write16(state, SIO_HI_RA_RAM_CMD__A, cmd);
982 ((state->m_hi_cfg_ctrl) &
993 status = read16(state, SIO_HI_RA_RAM_CMD__A,
998 status = read16(state, SIO_HI_RA_RAM_RES__A, p_result);
1007 static int hi_cfg_command(struct drxk_state *state)
1013 mutex_lock(&state->mutex);
1015 status = write16(state, SIO_HI_RA_RAM_PAR_6__A,
1016 state->m_hi_cfg_timeout);
1019 status = write16(state, SIO_HI_RA_RAM_PAR_5__A,
1020 state->m_hi_cfg_ctrl);
1023 status = write16(state, SIO_HI_RA_RAM_PAR_4__A,
1024 state->m_hi_cfg_wake_up_key);
1027 status = write16(state, SIO_HI_RA_RAM_PAR_3__A,
1028 state->m_hi_cfg_bridge_delay);
1031 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
1032 state->m_hi_cfg_timing_div);
1035 status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
1039 status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, NULL);
1043 state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
1045 mutex_unlock(&state->mutex);
1051 static int init_hi(struct drxk_state *state)
1055 state->m_hi_cfg_wake_up_key = (state->demod_address << 1);
1056 state->m_hi_cfg_timeout = 0x96FF;
1058 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE;
1060 return hi_cfg_command(state);
1063 static int mpegts_configure_pins(struct drxk_state *state, bool mpeg_enable)
1072 state->m_enable_parallel ? "parallel" : "serial");
1075 status = write16(state, SCU_RAM_GPIO__A,
1081 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
1087 status = write16(state, SIO_PDR_MSTRT_CFG__A, 0x0000);
1090 status = write16(state, SIO_PDR_MERR_CFG__A, 0x0000);
1093 status = write16(state, SIO_PDR_MCLK_CFG__A, 0x0000);
1096 status = write16(state, SIO_PDR_MVAL_CFG__A, 0x0000);
1099 status = write16(state, SIO_PDR_MD0_CFG__A, 0x0000);
1102 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1105 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1108 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1111 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1114 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1117 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1120 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1126 ((state->m_ts_data_strength <<
1128 sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength <<
1132 status = write16(state, SIO_PDR_MSTRT_CFG__A, sio_pdr_mdx_cfg);
1136 if (state->enable_merr_cfg)
1139 status = write16(state, SIO_PDR_MERR_CFG__A, err_cfg);
1142 status = write16(state, SIO_PDR_MVAL_CFG__A, err_cfg);
1146 if (state->m_enable_parallel) {
1148 status = write16(state, SIO_PDR_MD1_CFG__A,
1152 status = write16(state, SIO_PDR_MD2_CFG__A,
1156 status = write16(state, SIO_PDR_MD3_CFG__A,
1160 status = write16(state, SIO_PDR_MD4_CFG__A,
1164 status = write16(state, SIO_PDR_MD5_CFG__A,
1168 status = write16(state, SIO_PDR_MD6_CFG__A,
1172 status = write16(state, SIO_PDR_MD7_CFG__A,
1177 sio_pdr_mdx_cfg = ((state->m_ts_data_strength <<
1181 status = write16(state, SIO_PDR_MD1_CFG__A, 0x0000);
1184 status = write16(state, SIO_PDR_MD2_CFG__A, 0x0000);
1187 status = write16(state, SIO_PDR_MD3_CFG__A, 0x0000);
1190 status = write16(state, SIO_PDR_MD4_CFG__A, 0x0000);
1193 status = write16(state, SIO_PDR_MD5_CFG__A, 0x0000);
1196 status = write16(state, SIO_PDR_MD6_CFG__A, 0x0000);
1199 status = write16(state, SIO_PDR_MD7_CFG__A, 0x0000);
1203 status = write16(state, SIO_PDR_MCLK_CFG__A, sio_pdr_mclk_cfg);
1206 status = write16(state, SIO_PDR_MD0_CFG__A, sio_pdr_mdx_cfg);
1211 status = write16(state, SIO_PDR_MON_CFG__A, 0x0000);
1215 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
1222 static int mpegts_disable(struct drxk_state *state)
1226 return mpegts_configure_pins(state, false);
1229 static int bl_chain_cmd(struct drxk_state *state,
1237 mutex_lock(&state->mutex);
1238 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_CHAIN);
1241 status = write16(state, SIO_BL_CHAIN_ADDR__A, rom_offset);
1244 status = write16(state, SIO_BL_CHAIN_LEN__A, nr_of_elements);
1247 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
1254 status = read16(state, SIO_BL_STATUS__A, &bl_status);
1269 mutex_unlock(&state->mutex);
1274 static int download_microcode(struct drxk_state *state,
1327 status = write_block(state, address, block_size, p_src);
1338 static int dvbt_enable_ofdm_token_ring(struct drxk_state *state, bool enable)
1353 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1359 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, desired_ctrl);
1363 status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
1376 static int mpegts_stop(struct drxk_state *state)
1385 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1389 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1394 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode);
1398 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode);
1407 static int scu_command(struct drxk_state *state,
1430 mutex_lock(&state->mutex);
1443 write_block(state, SCU_RAM_PARAM_0__A -
1449 status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);
1464 status = read16(state, SCU_RAM_PARAM_0__A - ii,
1503 mutex_unlock(&state->mutex);
1507 static int set_iqm_af(struct drxk_state *state, bool active)
1515 status = read16(state, IQM_AF_STDBY__A, &data);
1533 status = write16(state, IQM_AF_STDBY__A, data);
1541 static int ctrl_power_mode(struct drxk_state *state, enum drx_power_mode *mode)
1574 if (state->m_current_power_mode == *mode)
1578 if (state->m_current_power_mode != DRX_POWER_UP) {
1579 status = power_up_device(state);
1582 status = dvbt_enable_ofdm_token_ring(state, true);
1599 switch (state->m_operation_mode) {
1601 status = mpegts_stop(state);
1604 status = power_down_dvbt(state, false);
1610 status = mpegts_stop(state);
1613 status = power_down_qam(state);
1620 status = dvbt_enable_ofdm_token_ring(state, false);
1623 status = write16(state, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode);
1626 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
1631 state->m_hi_cfg_ctrl |=
1633 status = hi_cfg_command(state);
1638 state->m_current_power_mode = *mode;
1647 static int power_down_dvbt(struct drxk_state *state, bool set_power_mode)
1656 status = read16(state, SCU_COMM_EXEC__A, &data);
1661 status = scu_command(state,
1668 status = scu_command(state,
1677 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
1680 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
1683 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
1688 status = set_iqm_af(state, false);
1694 status = ctrl_power_mode(state, &power_mode);
1704 static int setoperation_mode(struct drxk_state *state,
1717 status = write16(state, SCU_RAM_GPIO__A,
1723 if (state->m_operation_mode == o_mode)
1726 switch (state->m_operation_mode) {
1731 status = mpegts_stop(state);
1734 status = power_down_dvbt(state, true);
1737 state->m_operation_mode = OM_NONE;
1741 status = mpegts_stop(state);
1744 status = power_down_qam(state);
1747 state->m_operation_mode = OM_NONE;
1761 state->m_operation_mode = o_mode;
1762 status = set_dvbt_standard(state, o_mode);
1769 (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C');
1770 state->m_operation_mode = o_mode;
1771 status = set_qam_standard(state, o_mode);
1785 static int start(struct drxk_state *state, s32 offset_freq,
1794 if (state->m_drxk_state != DRXK_STOPPED &&
1795 state->m_drxk_state != DRXK_DTV_STARTED)
1798 state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON);
1801 state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect;
1805 switch (state->m_operation_mode) {
1809 status = set_qam(state, i_freqk_hz, offsetk_hz);
1812 state->m_drxk_state = DRXK_DTV_STARTED;
1816 status = mpegts_stop(state);
1819 status = set_dvbt(state, i_freqk_hz, offsetk_hz);
1822 status = dvbt_start(state);
1825 state->m_drxk_state = DRXK_DTV_STARTED;
1836 static int shut_down(struct drxk_state *state)
1840 mpegts_stop(state);
1844 static int get_lock_status(struct drxk_state *state, u32 *p_lock_status)
1856 switch (state->m_operation_mode) {
1860 status = get_qam_lock_status(state, p_lock_status);
1863 status = get_dvbt_lock_status(state, p_lock_status);
1867 state->m_operation_mode, __func__);
1876 static int mpegts_start(struct drxk_state *state)
1883 status = read16(state, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode);
1887 status = write16(state, FEC_OC_SNC_MODE__A, fec_oc_snc_mode);
1890 status = write16(state, FEC_OC_SNC_UNLOCK__A, 1);
1897 static int mpegts_dto_init(struct drxk_state *state)
1904 status = write16(state, FEC_OC_RCN_CTL_STEP_LO__A, 0x0000);
1907 status = write16(state, FEC_OC_RCN_CTL_STEP_HI__A, 0x000C);
1910 status = write16(state, FEC_OC_RCN_GAIN__A, 0x000A);
1913 status = write16(state, FEC_OC_AVR_PARM_A__A, 0x0008);
1916 status = write16(state, FEC_OC_AVR_PARM_B__A, 0x0006);
1919 status = write16(state, FEC_OC_TMD_HI_MARGIN__A, 0x0680);
1922 status = write16(state, FEC_OC_TMD_LO_MARGIN__A, 0x0080);
1925 status = write16(state, FEC_OC_TMD_COUNT__A, 0x03F4);
1930 status = write16(state, FEC_OC_OCR_INVERT__A, 0);
1933 status = write16(state, FEC_OC_SNC_LWM__A, 2);
1936 status = write16(state, FEC_OC_SNC_HWM__A, 12);
1944 static int mpegts_dto_setup(struct drxk_state *state,
1964 status = read16(state, FEC_OC_MODE__A, &fec_oc_reg_mode);
1967 status = read16(state, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode);
1972 if (state->m_insert_rs_byte) {
1983 if (!state->m_enable_parallel) {
1990 max_bit_rate = state->m_dvbt_bitrate;
1993 static_clk = state->m_dvbt_static_clk;
1999 max_bit_rate = state->m_dvbc_bitrate;
2000 static_clk = state->m_dvbc_static_clk;
2032 fec_oc_dto_period = (u16) (((state->m_sys_clock_freq)
2047 status = write16(state, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len);
2050 status = write16(state, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period);
2053 status = write16(state, FEC_OC_DTO_MODE__A, fec_oc_dto_mode);
2056 status = write16(state, FEC_OC_FCT_MODE__A, fec_oc_fct_mode);
2059 status = write16(state, FEC_OC_MODE__A, fec_oc_reg_mode);
2062 status = write16(state, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode);
2067 status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);
2070 status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,
2074 status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);
2081 static int mpegts_configure_polarity(struct drxk_state *state)
2096 if (state->m_invert_data)
2099 if (state->m_invert_err)
2102 if (state->m_invert_str)
2105 if (state->m_invert_val)
2108 if (state->m_invert_clk)
2111 return write16(state, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert);
2116 static int set_agc_rf(struct drxk_state *state,
2131 status = read16(state, IQM_AF_STDBY__A, &data);
2135 status = write16(state, IQM_AF_STDBY__A, data);
2138 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2146 if (state->m_rf_agc_pol)
2150 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2155 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2164 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2168 if (is_dvbt(state))
2169 p_if_agc_settings = &state->m_dvbt_if_agc_cfg;
2170 else if (is_qam(state))
2171 p_if_agc_settings = &state->m_qam_if_agc_cfg;
2173 p_if_agc_settings = &state->m_atv_if_agc_cfg;
2181 status = write16(state,
2189 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,
2195 status = write16(state, SCU_RAM_AGC_RF_MAX__A,
2204 status = read16(state, IQM_AF_STDBY__A, &data);
2208 status = write16(state, IQM_AF_STDBY__A, data);
2213 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2217 if (state->m_rf_agc_pol)
2221 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2226 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, 0);
2231 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,
2239 status = read16(state, IQM_AF_STDBY__A, &data);
2243 status = write16(state, IQM_AF_STDBY__A, data);
2248 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2252 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2269 static int set_agc_if(struct drxk_state *state,
2282 status = read16(state, IQM_AF_STDBY__A, &data);
2286 status = write16(state, IQM_AF_STDBY__A, data);
2290 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2298 if (state->m_if_agc_pol)
2302 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2307 status = read16(state, SCU_RAM_AGC_KI_RED__A, &data);
2315 status = write16(state, SCU_RAM_AGC_KI_RED__A, data);
2319 if (is_qam(state))
2320 p_rf_agc_settings = &state->m_qam_rf_agc_cfg;
2322 p_rf_agc_settings = &state->m_atv_rf_agc_cfg;
2326 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2335 status = read16(state, IQM_AF_STDBY__A, &data);
2339 status = write16(state, IQM_AF_STDBY__A, data);
2343 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2351 if (state->m_if_agc_pol)
2355 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2360 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
2369 status = read16(state, IQM_AF_STDBY__A, &data);
2373 status = write16(state, IQM_AF_STDBY__A, data);
2378 status = read16(state, SCU_RAM_AGC_CONFIG__A, &data);
2382 status = write16(state, SCU_RAM_AGC_CONFIG__A, data);
2390 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top);
2397 static int get_qam_signal_to_noise(struct drxk_state *state,
2412 status = read16(state, QAM_SL_ERR_POWER__A, &qam_sl_err_power);
2418 switch (state->props.modulation) {
2446 static int get_dvbt_signal_to_noise(struct drxk_state *state,
2466 status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,
2470 status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,
2474 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,
2478 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,
2488 status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_Q__A, ®_data);
2497 status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,
2550 static int get_signal_to_noise(struct drxk_state *state, s32 *p_signal_to_noise)
2555 switch (state->m_operation_mode) {
2557 return get_dvbt_signal_to_noise(state, p_signal_to_noise);
2560 return get_qam_signal_to_noise(state, p_signal_to_noise);
2568 static int get_dvbt_quality(struct drxk_state *state, s32 *p_quality)
2602 status = get_dvbt_signal_to_noise(state, &signal_to_noise);
2605 status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
2611 status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
2635 static int get_dvbc_quality(struct drxk_state *state, s32 *p_quality)
2647 status = get_qam_signal_to_noise(state, &signal_to_noise);
2651 switch (state->props.modulation) {
2682 static int get_quality(struct drxk_state *state, s32 *p_quality)
2686 switch (state->m_operation_mode) {
2688 return get_dvbt_quality(state, p_quality);
2690 return get_dvbc_quality(state, p_quality);
2712 static int ConfigureI2CBridge(struct drxk_state *state, bool b_enable_bridge)
2718 if (state->m_drxk_state == DRXK_UNINITIALIZED)
2720 if (state->m_drxk_state == DRXK_POWERED_DOWN)
2723 if (state->no_i2c_bridge)
2726 status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
2731 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2736 status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
2742 status = hi_command(state, SIO_HI_RA_RAM_CMD_BRDCTRL, NULL);
2750 static int set_pre_saw(struct drxk_state *state,
2761 status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference);
2768 static int bl_direct_cmd(struct drxk_state *state, u32 target_addr,
2779 mutex_lock(&state->mutex);
2780 status = write16(state, SIO_BL_MODE__A, SIO_BL_MODE_DIRECT);
2783 status = write16(state, SIO_BL_TGT_HDR__A, blockbank);
2786 status = write16(state, SIO_BL_TGT_ADDR__A, offset);
2789 status = write16(state, SIO_BL_SRC_ADDR__A, rom_offset);
2792 status = write16(state, SIO_BL_SRC_LEN__A, nr_of_elements);
2795 status = write16(state, SIO_BL_ENABLE__A, SIO_BL_ENABLE_ON);
2801 status = read16(state, SIO_BL_STATUS__A, &bl_status);
2814 mutex_unlock(&state->mutex);
2819 static int adc_sync_measurement(struct drxk_state *state, u16 *count)
2827 status = write16(state, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE);
2830 status = write16(state, IQM_AF_START_LOCK__A, 1);
2835 status = read16(state, IQM_AF_PHASE0__A, &data);
2840 status = read16(state, IQM_AF_PHASE1__A, &data);
2845 status = read16(state, IQM_AF_PHASE2__A, &data);
2857 static int adc_synchronization(struct drxk_state *state)
2864 status = adc_sync_measurement(state, &count);
2872 status = read16(state, IQM_AF_CLKNEG__A, &clk_neg);
2885 status = write16(state, IQM_AF_CLKNEG__A, clk_neg);
2888 status = adc_sync_measurement(state, &count);
2901 static int set_frequency_shifter(struct drxk_state *state,
2908 bool tuner_mirror = !state->m_b_mirror_freq_spect;
2913 u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3);
2924 if ((state->m_operation_mode == OM_QAM_ITU_A) ||
2925 (state->m_operation_mode == OM_QAM_ITU_C) ||
2926 (state->m_operation_mode == OM_DVBT))
2950 image_to_select = state->m_rfmirror ^ tuner_mirror ^
2952 state->m_iqm_fs_rate_ofs =
2956 state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1;
2960 status = write32(state, IQM_FS_RATE_OFS_LO__A,
2961 state->m_iqm_fs_rate_ofs);
2967 static int init_agc(struct drxk_state *state, bool is_dtv)
2997 if (!is_qam(state)) {
2999 __func__, state->m_operation_mode);
3017 fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay;
3019 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3024 status = write16(state, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode);
3027 status = write16(state, SCU_RAM_AGC_INGAIN_TGT__A, ingain_tgt);
3030 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, ingain_tgt_min);
3033 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);
3036 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,
3040 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
3044 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
3047 status = write16(state, SCU_RAM_AGC_IF_IACCU_LO__A, 0);
3050 status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, 0);
3053 status = write16(state, SCU_RAM_AGC_RF_IACCU_LO__A, 0);
3056 status = write16(state, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max);
3059 status = write16(state, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max);
3063 status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,
3067 status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,
3071 status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);
3075 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MAX__A, 1023);
3078 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023);
3081 status = write16(state, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50);
3085 status = write16(state, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20);
3088 status = write16(state, SCU_RAM_AGC_CLP_SUM_MIN__A, clp_sum_min);
3091 status = write16(state, SCU_RAM_AGC_SNS_SUM_MIN__A, sns_sum_min);
3094 status = write16(state, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to);
3097 status = write16(state, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to);
3100 status = write16(state, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff);
3103 status = write16(state, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0);
3106 status = write16(state, SCU_RAM_AGC_KI_MIN__A, 0x0117);
3109 status = write16(state, SCU_RAM_AGC_KI_MAX__A, 0x0657);
3112 status = write16(state, SCU_RAM_AGC_CLP_SUM__A, 0);
3115 status = write16(state, SCU_RAM_AGC_CLP_CYCCNT__A, 0);
3118 status = write16(state, SCU_RAM_AGC_CLP_DIR_WD__A, 0);
3121 status = write16(state, SCU_RAM_AGC_CLP_DIR_STP__A, 1);
3124 status = write16(state, SCU_RAM_AGC_SNS_SUM__A, 0);
3127 status = write16(state, SCU_RAM_AGC_SNS_CYCCNT__A, 0);
3130 status = write16(state, SCU_RAM_AGC_SNS_DIR_WD__A, 0);
3133 status = write16(state, SCU_RAM_AGC_SNS_DIR_STP__A, 1);
3136 status = write16(state, SCU_RAM_AGC_SNS_CYCLEN__A, 500);
3139 status = write16(state, SCU_RAM_AGC_KI_CYCLEN__A, 500);
3144 status = read16(state, SCU_RAM_AGC_KI__A, &data);
3154 status = write16(state, SCU_RAM_AGC_KI__A, data);
3161 static int dvbtqam_get_acc_pkt_err(struct drxk_state *state, u16 *packet_err)
3167 status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
3169 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,
3176 static int dvbt_sc_command(struct drxk_state *state,
3188 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_exec);
3200 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3212 status = write16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, subcmd);
3231 status |= write16(state, OFDM_SC_RA_RAM_PARAM1__A, param1);
3235 status |= write16(state, OFDM_SC_RA_RAM_PARAM0__A, param0);
3240 status |= write16(state, OFDM_SC_RA_RAM_CMD__A, cmd);
3253 status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
3260 status = read16(state, OFDM_SC_RA_RAM_CMD_ADDR__A, &err_code);
3277 status = read16(state, OFDM_SC_RA_RAM_PARAM0__A, &(param0));
3298 static int power_up_dvbt(struct drxk_state *state)
3304 status = ctrl_power_mode(state, &power_mode);
3310 static int dvbt_ctrl_set_inc_enable(struct drxk_state *state, bool *enabled)
3316 status = write16(state, IQM_CF_BYPASSDET__A, 0);
3318 status = write16(state, IQM_CF_BYPASSDET__A, 1);
3325 static int dvbt_ctrl_set_fr_enable(struct drxk_state *state, bool *enabled)
3333 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A,
3337 status = write16(state, OFDM_SC_RA_RAM_FR_THRES_8K__A, 0);
3345 static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state,
3352 status = read16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, &data);
3373 status = write16(state, OFDM_SC_RA_RAM_ECHO_THRES__A, data);
3380 static int dvbt_ctrl_set_sqi_speed(struct drxk_state *state,
3395 status = write16(state, SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A,
3413 static int dvbt_activate_presets(struct drxk_state *state)
3423 status = dvbt_ctrl_set_inc_enable(state, &setincenable);
3426 status = dvbt_ctrl_set_fr_enable(state, &setfrenable);
3429 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres2k);
3432 status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);
3435 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,
3436 state->m_dvbt_if_agc_cfg.ingain_tgt_max);
3453 static int set_dvbt_standard(struct drxk_state *state,
3462 power_up_dvbt(state);
3464 switch_antenna_to_dvbt(state);
3466 status = scu_command(state,
3474 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3481 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3484 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3487 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
3493 status = write16(state, IQM_AF_UPD_SEL__A, 1);
3497 status = write16(state, IQM_AF_CLP_LEN__A, 0);
3501 status = write16(state, IQM_AF_SNS_LEN__A, 0);
3505 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
3508 status = set_iqm_af(state, true);
3512 status = write16(state, IQM_AF_AGC_RF__A, 0);
3517 status = write16(state, IQM_AF_INC_LCT__A, 0); /* crunch in IQM_CF */
3520 status = write16(state, IQM_CF_DET_LCT__A, 0); /* detect in IQM_CF */
3523 status = write16(state, IQM_CF_WND_LEN__A, 3); /* peak detector window length */
3527 status = write16(state, IQM_RC_STRETCH__A, 16);
3530 status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
3533 status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
3536 status = write16(state, IQM_CF_SCALE__A, 1600);
3539 status = write16(state, IQM_CF_SCALE_SH__A, 0);
3544 status = write16(state, IQM_AF_CLP_TH__A, 448);
3547 status = write16(state, IQM_CF_DATATH__A, 495); /* crunching threshold */
3551 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,
3556 status = write16(state, IQM_CF_PKDTH__A, 2); /* peak detector threshold */
3559 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 2);
3563 status = write16(state, IQM_CF_COMM_INT_MSK__A, 1);
3566 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
3571 status = adc_synchronization(state);
3574 status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg);
3579 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3583 status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true);
3586 status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true);
3591 status = read16(state, OFDM_SC_RA_RAM_CONFIG__A, &data);
3595 status = write16(state, OFDM_SC_RA_RAM_CONFIG__A, data);
3600 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3604 if (!state->m_drxk_a3_rom_code) {
3606 status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
3607 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay);
3614 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_DELAY__A, 1);
3617 status = write16(state, OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A, 2);
3623 status = write16(state, FEC_DI_INPUT_CTL__A, 1); /* OFDM input */
3629 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x400);
3633 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, 0x1000);
3637 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, 0x0001);
3642 status = mpegts_dto_setup(state, OM_DVBT);
3646 status = dvbt_activate_presets(state);
3662 static int dvbt_start(struct drxk_state *state)
3672 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,
3678 status = mpegts_start(state);
3681 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
3699 static int set_dvbt(struct drxk_state *state, u16 intermediate_freqk_hz,
3712 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
3719 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
3724 status = write16(state, OFDM_SC_COMM_EXEC__A, OFDM_SC_COMM_EXEC_STOP);
3727 status = write16(state, OFDM_LC_COMM_EXEC__A, OFDM_LC_COMM_EXEC_STOP);
3733 status = write16(state, OFDM_CP_COMM_EXEC__A, OFDM_CP_COMM_EXEC_STOP);
3740 switch (state->props.transmission_mode) {
3752 switch (state->props.guard_interval) {
3770 switch (state->props.hierarchy) {
3787 switch (state->props.modulation) {
3822 status = write16(state, OFDM_EC_SB_PRIOR__A, OFDM_EC_SB_PRIOR_HI);
3828 switch (state->props.code_rate_HP) {
3861 switch (state->props.bandwidth_hz) {
3863 state->props.bandwidth_hz = 8000000;
3867 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3872 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3876 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3880 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3884 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3891 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3896 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3900 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3904 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3908 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3915 status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
3920 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
3924 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
3928 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
3932 status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
3956 ((state->m_sys_clock_freq *
3969 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate_ofs);
3980 status = set_frequency_shifter(state, intermediate_freqk_hz,
3988 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
3993 status = write16(state, OFDM_SC_COMM_STATE__A, 0);
3996 status = write16(state, OFDM_SC_COMM_EXEC__A, 1);
4001 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
4013 status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM,
4018 if (!state->m_drxk_a3_rom_code)
4019 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed);
4037 static int get_dvbt_lock_status(struct drxk_state *state, u32 *p_lock_status)
4053 status = read16(state, OFDM_SC_COMM_EXEC__A, &sc_comm_exec);
4059 status = read16(state, OFDM_SC_RA_RAM_LOCK__A, &sc_ra_ram_lock);
4078 static int power_up_qam(struct drxk_state *state)
4084 status = ctrl_power_mode(state, &power_mode);
4093 static int power_down_qam(struct drxk_state *state)
4100 status = read16(state, SCU_COMM_EXEC__A, &data);
4109 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
4112 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
4119 status = set_iqm_af(state, false);
4141 static int set_qam_measurement(struct drxk_state *state,
4202 status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);
4205 status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,
4209 status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);
4216 static int set_qam16(struct drxk_state *state)
4223 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13517);
4226 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 13517);
4229 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 13517);
4232 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13517);
4235 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13517);
4238 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 13517);
4242 status = write16(state, QAM_DQ_QUAL_FUN0__A, 2);
4245 status = write16(state, QAM_DQ_QUAL_FUN1__A, 2);
4248 status = write16(state, QAM_DQ_QUAL_FUN2__A, 2);
4251 status = write16(state, QAM_DQ_QUAL_FUN3__A, 2);
4254 status = write16(state, QAM_DQ_QUAL_FUN4__A, 2);
4257 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4261 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4264 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4267 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4272 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4278 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4281 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4284 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4287 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4290 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4293 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4296 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4299 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4303 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4306 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4309 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4312 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4315 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4318 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4321 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4324 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4327 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 32);
4330 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4333 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4336 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4343 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 140);
4346 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4349 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 95);
4352 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 120);
4355 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 230);
4358 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 105);
4362 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4365 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4368 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 24);
4375 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 16);
4378 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 220);
4381 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 25);
4384 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 6);
4387 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24);
4390 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65);
4393 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127);
4410 static int set_qam32(struct drxk_state *state)
4418 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6707);
4421 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6707);
4424 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6707);
4427 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6707);
4430 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6707);
4433 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 6707);
4438 status = write16(state, QAM_DQ_QUAL_FUN0__A, 3);
4441 status = write16(state, QAM_DQ_QUAL_FUN1__A, 3);
4444 status = write16(state, QAM_DQ_QUAL_FUN2__A, 3);
4447 status = write16(state, QAM_DQ_QUAL_FUN3__A, 3);
4450 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4453 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4457 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4460 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4463 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4469 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4477 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4480 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4483 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4486 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4489 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4492 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4495 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4498 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4502 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4505 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20);
4508 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 80);
4511 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4514 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20);
4517 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4520 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4523 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 16);
4526 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 16);
4529 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4532 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4535 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4542 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 90);
4545 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 50);
4548 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4551 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4554 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 170);
4557 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4561 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4564 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4567 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 10);
4574 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4577 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 140);
4580 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8);
4583 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16);
4586 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26);
4589 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56);
4592 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86);
4606 static int set_qam64(struct drxk_state *state)
4613 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 13336);
4616 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12618);
4619 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 11988);
4622 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 13809);
4625 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13809);
4628 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15609);
4633 status = write16(state, QAM_DQ_QUAL_FUN0__A, 4);
4636 status = write16(state, QAM_DQ_QUAL_FUN1__A, 4);
4639 status = write16(state, QAM_DQ_QUAL_FUN2__A, 4);
4642 status = write16(state, QAM_DQ_QUAL_FUN3__A, 4);
4645 status = write16(state, QAM_DQ_QUAL_FUN4__A, 3);
4648 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4652 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
4655 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
4658 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4663 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4671 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4674 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4677 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4680 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4683 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4686 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4689 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4692 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4696 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4699 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30);
4702 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 100);
4705 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4708 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 30);
4711 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 50);
4714 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4717 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4720 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
4723 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4726 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4729 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
4736 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 100);
4739 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4742 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4745 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 110);
4748 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 200);
4751 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 95);
4755 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4758 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
4761 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 15);
4768 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 12);
4771 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 141);
4774 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 7);
4777 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 0);
4780 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15);
4783 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45);
4786 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80);
4801 static int set_qam128(struct drxk_state *state)
4808 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 6564);
4811 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 6598);
4814 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 6394);
4817 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 6409);
4820 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 6656);
4823 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 7238);
4828 status = write16(state, QAM_DQ_QUAL_FUN0__A, 6);
4831 status = write16(state, QAM_DQ_QUAL_FUN1__A, 6);
4834 status = write16(state, QAM_DQ_QUAL_FUN2__A, 6);
4837 status = write16(state, QAM_DQ_QUAL_FUN3__A, 6);
4840 status = write16(state, QAM_DQ_QUAL_FUN4__A, 5);
4843 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
4847 status = write16(state, QAM_SY_SYNC_HWM__A, 6);
4850 status = write16(state, QAM_SY_SYNC_AWM__A, 5);
4853 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
4860 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
4868 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
4871 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
4874 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
4877 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
4880 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
4883 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
4886 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
4889 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
4893 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
4896 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40);
4899 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 120);
4902 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
4905 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 40);
4908 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 60);
4911 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
4914 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
4917 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 64);
4920 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
4923 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
4926 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 0);
4933 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
4936 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
4939 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
4942 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
4945 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 140);
4948 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 100);
4952 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
4955 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 5);
4959 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
4965 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
4968 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 65);
4971 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 5);
4974 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 3);
4977 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1);
4980 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12);
4983 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23);
4998 static int set_qam256(struct drxk_state *state)
5005 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD0__A, 11502);
5008 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD1__A, 12084);
5011 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD2__A, 12543);
5014 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD3__A, 12931);
5017 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD4__A, 13629);
5020 status = write16(state, SCU_RAM_QAM_EQ_CMA_RAD5__A, 15385);
5025 status = write16(state, QAM_DQ_QUAL_FUN0__A, 8);
5028 status = write16(state, QAM_DQ_QUAL_FUN1__A, 8);
5031 status = write16(state, QAM_DQ_QUAL_FUN2__A, 8);
5034 status = write16(state, QAM_DQ_QUAL_FUN3__A, 8);
5037 status = write16(state, QAM_DQ_QUAL_FUN4__A, 6);
5040 status = write16(state, QAM_DQ_QUAL_FUN5__A, 0);
5044 status = write16(state, QAM_SY_SYNC_HWM__A, 5);
5047 status = write16(state, QAM_SY_SYNC_AWM__A, 4);
5050 status = write16(state, QAM_SY_SYNC_LWM__A, 3);
5056 status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
5064 status = write16(state, SCU_RAM_QAM_LC_CA_FINE__A, 15);
5067 status = write16(state, SCU_RAM_QAM_LC_CA_COARSE__A, 40);
5070 status = write16(state, SCU_RAM_QAM_LC_EP_FINE__A, 12);
5073 status = write16(state, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24);
5076 status = write16(state, SCU_RAM_QAM_LC_EP_COARSE__A, 24);
5079 status = write16(state, SCU_RAM_QAM_LC_EI_FINE__A, 12);
5082 status = write16(state, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16);
5085 status = write16(state, SCU_RAM_QAM_LC_EI_COARSE__A, 16);
5089 status = write16(state, SCU_RAM_QAM_LC_CP_FINE__A, 5);
5092 status = write16(state, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50);
5095 status = write16(state, SCU_RAM_QAM_LC_CP_COARSE__A, 250);
5098 status = write16(state, SCU_RAM_QAM_LC_CI_FINE__A, 5);
5101 status = write16(state, SCU_RAM_QAM_LC_CI_MEDIUM__A, 50);
5104 status = write16(state, SCU_RAM_QAM_LC_CI_COARSE__A, 125);
5107 status = write16(state, SCU_RAM_QAM_LC_CF_FINE__A, 16);
5110 status = write16(state, SCU_RAM_QAM_LC_CF_MEDIUM__A, 25);
5113 status = write16(state, SCU_RAM_QAM_LC_CF_COARSE__A, 48);
5116 status = write16(state, SCU_RAM_QAM_LC_CF1_FINE__A, 5);
5119 status = write16(state, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 10);
5122 status = write16(state, SCU_RAM_QAM_LC_CF1_COARSE__A, 10);
5129 status = write16(state, SCU_RAM_QAM_FSM_RTH__A, 50);
5132 status = write16(state, SCU_RAM_QAM_FSM_FTH__A, 60);
5135 status = write16(state, SCU_RAM_QAM_FSM_CTH__A, 80);
5138 status = write16(state, SCU_RAM_QAM_FSM_PTH__A, 100);
5141 status = write16(state, SCU_RAM_QAM_FSM_QTH__A, 150);
5144 status = write16(state, SCU_RAM_QAM_FSM_MTH__A, 110);
5148 status = write16(state, SCU_RAM_QAM_FSM_RATE_LIM__A, 40);
5151 status = write16(state, SCU_RAM_QAM_FSM_COUNT_LIM__A, 4);
5154 status = write16(state, SCU_RAM_QAM_FSM_FREQ_LIM__A, 12);
5161 status = write16(state, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, (u16) 8);
5164 status = write16(state, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, (u16) 74);
5167 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) 18);
5170 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) 13);
5173 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) 7);
5176 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) 0);
5179 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8);
5194 static int qam_reset_qam(struct drxk_state *state)
5201 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
5205 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5222 static int qam_set_symbolrate(struct drxk_state *state)
5233 adc_frequency = (state->m_sys_clock_freq * 1000) / 3;
5235 if (state->props.symbol_rate <= 1188750)
5237 else if (state->props.symbol_rate <= 2377500)
5239 else if (state->props.symbol_rate <= 4755000)
5241 status = write16(state, IQM_FD_RATESEL__A, ratesel);
5248 symb_freq = state->props.symbol_rate * (1 << ratesel);
5257 status = write32(state, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate);
5260 state->m_iqm_rc_rate = iqm_rc_rate;
5264 symb_freq = state->props.symbol_rate;
5275 status = write16(state, QAM_LC_SYMBOL_FREQ__A, (u16) lc_symb_rate);
5292 static int get_qam_lock_status(struct drxk_state *state, u32 *p_lock_status)
5299 status = scu_command(state,
5333 static int qam_demodulator_command(struct drxk_state *state,
5340 set_param_parameters[0] = state->m_constellation; /* modulation */
5346 if (state->m_operation_mode == OM_QAM_ITU_C)
5351 status = scu_command(state,
5358 status = scu_command(state,
5364 if (state->m_operation_mode == OM_QAM_ITU_C)
5374 status = scu_command(state,
5391 static int set_qam(struct drxk_state *state, u16 intermediate_freqk_hz,
5396 int qam_demod_param_count = state->qam_demod_parameter_count;
5405 status = write16(state, FEC_DI_COMM_EXEC__A, FEC_DI_COMM_EXEC_STOP);
5408 status = write16(state, FEC_RS_COMM_EXEC__A, FEC_RS_COMM_EXEC_STOP);
5411 status = qam_reset_qam(state);
5420 status = qam_set_symbolrate(state);
5425 switch (state->props.modulation) {
5427 state->m_constellation = DRX_CONSTELLATION_QAM256;
5431 state->m_constellation = DRX_CONSTELLATION_QAM64;
5434 state->m_constellation = DRX_CONSTELLATION_QAM16;
5437 state->m_constellation = DRX_CONSTELLATION_QAM32;
5440 state->m_constellation = DRX_CONSTELLATION_QAM128;
5451 if (state->qam_demod_parameter_count == 4
5452 || !state->qam_demod_parameter_count) {
5454 status = qam_demodulator_command(state, qam_demod_param_count);
5460 if (state->qam_demod_parameter_count == 2
5461 || (!state->qam_demod_parameter_count && status < 0)) {
5463 status = qam_demodulator_command(state, qam_demod_param_count);
5470 state->qam_demod_parameter_count,
5471 state->microcode_name);
5473 } else if (!state->qam_demod_parameter_count) {
5482 state->qam_demod_parameter_count = qam_demod_param_count;
5494 status = set_frequency_shifter(state, intermediate_freqk_hz,
5500 status = set_qam_measurement(state, state->m_constellation,
5501 state->props.symbol_rate);
5506 status = write16(state, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE);
5509 status = write16(state, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE);
5514 status = write16(state, QAM_LC_RATE_LIMIT__A, 3);
5517 status = write16(state, QAM_LC_LPF_FACTORP__A, 4);
5520 status = write16(state, QAM_LC_LPF_FACTORI__A, 4);
5523 status = write16(state, QAM_LC_MODE__A, 7);
5527 status = write16(state, QAM_LC_QUAL_TAB0__A, 1);
5530 status = write16(state, QAM_LC_QUAL_TAB1__A, 1);
5533 status = write16(state, QAM_LC_QUAL_TAB2__A, 1);
5536 status = write16(state, QAM_LC_QUAL_TAB3__A, 1);
5539 status = write16(state, QAM_LC_QUAL_TAB4__A, 2);
5542 status = write16(state, QAM_LC_QUAL_TAB5__A, 2);
5545 status = write16(state, QAM_LC_QUAL_TAB6__A, 2);
5548 status = write16(state, QAM_LC_QUAL_TAB8__A, 2);
5551 status = write16(state, QAM_LC_QUAL_TAB9__A, 2);
5554 status = write16(state, QAM_LC_QUAL_TAB10__A, 2);
5557 status = write16(state, QAM_LC_QUAL_TAB12__A, 2);
5560 status = write16(state, QAM_LC_QUAL_TAB15__A, 3);
5563 status = write16(state, QAM_LC_QUAL_TAB16__A, 3);
5566 status = write16(state, QAM_LC_QUAL_TAB20__A, 4);
5569 status = write16(state, QAM_LC_QUAL_TAB25__A, 4);
5574 status = write16(state, QAM_SY_SP_INV__A,
5580 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5585 switch (state->props.modulation) {
5587 status = set_qam16(state);
5590 status = set_qam32(state);
5594 status = set_qam64(state);
5597 status = set_qam128(state);
5600 status = set_qam256(state);
5610 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5617 status = mpegts_dto_setup(state, state->m_operation_mode);
5622 status = mpegts_start(state);
5625 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE);
5628 status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE);
5631 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_ACTIVE);
5636 status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
5651 static int set_qam_standard(struct drxk_state *state,
5664 switch_antenna_to_qam(state);
5667 status = power_up_qam(state);
5671 status = qam_reset_qam(state);
5677 status = write16(state, IQM_COMM_EXEC__A, IQM_COMM_EXEC_B_STOP);
5680 status = write16(state, IQM_AF_AMUX__A, IQM_AF_AMUX_SIGNAL2ADC);
5688 status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,
5693 status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,
5699 status = bl_direct_cmd(state,
5711 status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);
5714 status = write16(state, IQM_CF_SYMMETRIC__A, 0);
5717 status = write16(state, IQM_CF_MIDTAP__A,
5722 status = write16(state, IQM_RC_STRETCH__A, 21);
5725 status = write16(state, IQM_AF_CLP_LEN__A, 0);
5728 status = write16(state, IQM_AF_CLP_TH__A, 448);
5731 status = write16(state, IQM_AF_SNS_LEN__A, 0);
5734 status = write16(state, IQM_CF_POW_MEAS_LEN__A, 0);
5738 status = write16(state, IQM_FS_ADJ_SEL__A, 1);
5741 status = write16(state, IQM_RC_ADJ_SEL__A, 1);
5744 status = write16(state, IQM_CF_ADJ_SEL__A, 1);
5747 status = write16(state, IQM_AF_UPD_SEL__A, 0);
5752 status = write16(state, IQM_CF_CLP_VAL__A, 500);
5755 status = write16(state, IQM_CF_DATATH__A, 1000);
5758 status = write16(state, IQM_CF_BYPASSDET__A, 1);
5761 status = write16(state, IQM_CF_DET_LCT__A, 0);
5764 status = write16(state, IQM_CF_WND_LEN__A, 1);
5767 status = write16(state, IQM_CF_PKDTH__A, 1);
5770 status = write16(state, IQM_AF_INC_BYPASS__A, 1);
5775 status = set_iqm_af(state, true);
5778 status = write16(state, IQM_AF_START_LOCK__A, 0x01);
5783 status = adc_synchronization(state);
5788 status = write16(state, SCU_RAM_QAM_FSM_STEP_PERIOD__A, 2000);
5793 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_HOLD);
5800 status = init_agc(state, true);
5803 status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg));
5808 status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true);
5811 status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true);
5816 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
5823 static int write_gpio(struct drxk_state *state)
5830 status = write16(state, SCU_RAM_GPIO__A,
5836 status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
5840 if (state->m_has_sawsw) {
5841 if (state->uio_mask & 0x0001) { /* UIO-1 */
5843 status = write16(state, SIO_PDR_SMA_TX_CFG__A,
5844 state->m_gpio_cfg);
5849 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5852 if ((state->m_gpio & 0x0001) == 0)
5857 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5861 if (state->uio_mask & 0x0002) { /* UIO-2 */
5863 status = write16(state, SIO_PDR_SMA_RX_CFG__A,
5864 state->m_gpio_cfg);
5869 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5872 if ((state->m_gpio & 0x0002) == 0)
5877 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5881 if (state->uio_mask & 0x0004) { /* UIO-3 */
5883 status = write16(state, SIO_PDR_GPIO_CFG__A,
5884 state->m_gpio_cfg);
5889 status = read16(state, SIO_PDR_UIO_OUT_LO__A, &value);
5892 if ((state->m_gpio & 0x0004) == 0)
5897 status = write16(state, SIO_PDR_UIO_OUT_LO__A, value);
5903 status = write16(state, SIO_TOP_COMM_KEY__A, 0x0000);
5910 static int switch_antenna_to_qam(struct drxk_state *state)
5917 if (!state->antenna_gpio)
5920 gpio_state = state->m_gpio & state->antenna_gpio;
5922 if (state->antenna_dvbt ^ gpio_state) {
5924 if (state->antenna_dvbt)
5925 state->m_gpio &= ~state->antenna_gpio;
5927 state->m_gpio |= state->antenna_gpio;
5928 status = write_gpio(state);
5935 static int switch_antenna_to_dvbt(struct drxk_state *state)
5942 if (!state->antenna_gpio)
5945 gpio_state = state->m_gpio & state->antenna_gpio;
5947 if (!(state->antenna_dvbt ^ gpio_state)) {
5949 if (state->antenna_dvbt)
5950 state->m_gpio |= state->antenna_gpio;
5952 state->m_gpio &= ~state->antenna_gpio;
5953 status = write_gpio(state);
5961 static int power_down_device(struct drxk_state *state)
5972 if (state->m_b_p_down_open_bridge) {
5974 status = ConfigureI2CBridge(state, true);
5979 status = dvbt_enable_ofdm_token_ring(state, false);
5983 status = write16(state, SIO_CC_PWD_MODE__A,
5987 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
5990 state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ;
5991 status = hi_cfg_command(state);
5999 static int init_drxk(struct drxk_state *state)
6006 if (state->m_drxk_state == DRXK_UNINITIALIZED) {
6007 drxk_i2c_lock(state);
6008 status = power_up_device(state);
6011 status = drxx_open(state);
6015 status = write16(state, SIO_CC_SOFT_RST__A,
6021 status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
6029 state->m_drxk_a3_patch_code = true;
6030 status = get_device_capabilities(state);
6037 state->m_hi_cfg_bridge_delay =
6038 (u16) ((state->m_osc_clock_freq / 1000) *
6041 if (state->m_hi_cfg_bridge_delay >
6043 state->m_hi_cfg_bridge_delay =
6047 state->m_hi_cfg_bridge_delay +=
6048 state->m_hi_cfg_bridge_delay <<
6051 status = init_hi(state);
6056 if (!(state->m_DRXK_A1_ROM_CODE)
6057 && !(state->m_DRXK_A2_ROM_CODE))
6060 status = write16(state, SCU_RAM_GPIO__A,
6067 status = mpegts_disable(state);
6072 status = write16(state, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP);
6075 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP);
6080 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6086 status = write16(state, SIO_BL_COMM_EXEC__A,
6090 status = bl_chain_cmd(state, 0, 6, 100);
6094 if (state->fw) {
6095 status = download_microcode(state, state->fw->data,
6096 state->fw->size);
6102 status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
6108 status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
6111 status = drxx_open(state);
6118 status = ctrl_power_mode(state, &power_mode);
6133 status = write16(state, SCU_RAM_DRIVER_VER_HI__A,
6142 status = write16(state, SCU_RAM_DRIVER_VER_LO__A,
6162 status = write16(state, SCU_RAM_DRIVER_DEBUG__A, 0);
6168 status = write16(state, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP);
6172 status = mpegts_dto_init(state);
6175 status = mpegts_stop(state);
6178 status = mpegts_configure_polarity(state);
6181 status = mpegts_configure_pins(state, state->m_enable_mpeg_output);
6185 status = write_gpio(state);
6189 state->m_drxk_state = DRXK_STOPPED;
6191 if (state->m_b_power_down) {
6192 status = power_down_device(state);
6195 state->m_drxk_state = DRXK_POWERED_DOWN;
6197 state->m_drxk_state = DRXK_STOPPED;
6201 if (state->m_has_dvbc) {
6202 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A;
6203 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C;
6204 strlcat(state->frontend.ops.info.name, " DVB-C",
6205 sizeof(state->frontend.ops.info.name));
6207 if (state->m_has_dvbt) {
6208 state->frontend.ops.delsys[n++] = SYS_DVBT;
6209 strlcat(state->frontend.ops.info.name, " DVB-T",
6210 sizeof(state->frontend.ops.info.name));
6212 drxk_i2c_unlock(state);
6216 state->m_drxk_state = DRXK_NO_DEV;
6217 drxk_i2c_unlock(state);
6227 struct drxk_state *state = context;
6232 state->microcode_name);
6234 state->microcode_name);
6235 state->microcode_name = NULL;
6248 state->fw = fw;
6250 init_drxk(state);
6255 struct drxk_state *state = fe->demodulator_priv;
6258 release_firmware(state->fw);
6260 kfree(state);
6265 struct drxk_state *state = fe->demodulator_priv;
6269 if (state->m_drxk_state == DRXK_NO_DEV)
6271 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6274 shut_down(state);
6280 struct drxk_state *state = fe->demodulator_priv;
6284 if (state->m_drxk_state == DRXK_NO_DEV)
6287 return ConfigureI2CBridge(state, enable ? true : false);
6294 struct drxk_state *state = fe->demodulator_priv;
6299 if (state->m_drxk_state == DRXK_NO_DEV)
6302 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6317 old_delsys = state->props.delivery_system;
6318 state->props = *p;
6321 shut_down(state);
6325 if (!state->m_has_dvbc)
6327 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ?
6329 if (state->m_itut_annex_c)
6330 setoperation_mode(state, OM_QAM_ITU_C);
6332 setoperation_mode(state, OM_QAM_ITU_A);
6335 if (!state->m_has_dvbt)
6337 setoperation_mode(state, OM_DVBT);
6345 start(state, 0, IF);
6362 static int get_strength(struct drxk_state *state, u64 *strength)
6377 if (is_dvbt(state)) {
6378 rf_agc = state->m_dvbt_rf_agc_cfg;
6379 if_agc = state->m_dvbt_if_agc_cfg;
6380 } else if (is_qam(state)) {
6381 rf_agc = state->m_qam_rf_agc_cfg;
6382 if_agc = state->m_qam_if_agc_cfg;
6384 rf_agc = state->m_atv_rf_agc_cfg;
6385 if_agc = state->m_atv_if_agc_cfg;
6390 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI__A, &scu_lvl);
6395 status = read16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, &scu_coc);
6423 status = read16(state, SCU_RAM_AGC_IF_IACCU_HI__A,
6428 status = read16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A,
6466 struct drxk_state *state = fe->demodulator_priv;
6479 if (state->m_drxk_state == DRXK_NO_DEV)
6481 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6485 state->fe_status = 0;
6486 get_lock_status(state, &stat);
6488 state->fe_status |= 0x1f;
6490 state->fe_status |= 0x0f;
6492 state->fe_status |= 0x07;
6497 get_strength(state, &c->strength.stat[0].uvalue);
6502 get_signal_to_noise(state, &cnr);
6530 status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, ®16);
6535 status = read16(state, OFDM_EC_VD_IN_BIT_CNT__A , ®16);
6541 status = read16(state, FEC_RS_NR_BIT_ERRORS__A, ®16);
6546 status = read16(state, FEC_RS_MEASUREMENT_PRESCALE__A, ®16);
6551 status = read16(state, FEC_RS_MEASUREMENT_PERIOD__A, ®16);
6556 status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, ®16);
6560 write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
6589 struct drxk_state *state = fe->demodulator_priv;
6598 *status = state->fe_status;
6606 struct drxk_state *state = fe->demodulator_priv;
6611 if (state->m_drxk_state == DRXK_NO_DEV)
6613 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6622 struct drxk_state *state = fe->demodulator_priv;
6627 if (state->m_drxk_state == DRXK_NO_DEV)
6629 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6632 get_signal_to_noise(state, &snr2);
6643 struct drxk_state *state = fe->demodulator_priv;
6648 if (state->m_drxk_state == DRXK_NO_DEV)
6650 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6653 dvbtqam_get_acc_pkt_err(state, &err);
6661 struct drxk_state *state = fe->demodulator_priv;
6666 if (state->m_drxk_state == DRXK_NO_DEV)
6668 if (state->m_drxk_state == DRXK_UNINITIALIZED)
6721 struct drxk_state *state = NULL;
6726 state = kzalloc(sizeof(struct drxk_state), GFP_KERNEL);
6727 if (!state)
6730 state->i2c = i2c;
6731 state->demod_address = adr;
6732 state->single_master = config->single_master;
6733 state->microcode_name = config->microcode_name;
6734 state->qam_demod_parameter_count = config->qam_demod_parameter_count;
6735 state->no_i2c_bridge = config->no_i2c_bridge;
6736 state->antenna_gpio = config->antenna_gpio;
6737 state->antenna_dvbt = config->antenna_dvbt;
6738 state->m_chunk_size = config->chunk_size;
6739 state->enable_merr_cfg = config->enable_merr_cfg;
6742 state->m_dvbt_static_clk = false;
6743 state->m_dvbc_static_clk = false;
6745 state->m_dvbt_static_clk = true;
6746 state->m_dvbc_static_clk = true;
6751 state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07;
6753 state->m_ts_clockk_strength = 0x06;
6756 state->m_enable_parallel = true;
6758 state->m_enable_parallel = false;
6761 state->uio_mask = config->antenna_gpio;
6764 if (!state->antenna_dvbt && state->antenna_gpio)
6765 state->m_gpio |= state->antenna_gpio;
6767 state->m_gpio &= ~state->antenna_gpio;
6769 mutex_init(&state->mutex);
6771 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops));
6772 state->frontend.demodulator_priv = state;
6774 init_state(state);
6777 if (state->microcode_name) {
6780 status = request_firmware(&fw, state->microcode_name,
6781 state->i2c->dev.parent);
6784 load_firmware_cb(fw, state);
6785 } else if (init_drxk(state) < 0)
6790 p = &state->frontend.dtv_property_cache;
6810 return &state->frontend;
6814 kfree(state);