Lines Matching refs:status
317 int status = 0;
322 while (!status) {
335 status = WriteBlock(state, Address, Length * 2, pTable, 0);
338 return status;
357 int status;
361 status = WriteTable(state, state->m_InitCE);
362 if (status < 0)
370 status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
371 if (status < 0)
374 status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
375 if (status < 0)
378 status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
379 if (status < 0)
382 status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
383 if (status < 0)
388 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
389 if (status < 0)
392 return status;
397 int status = 0;
405 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
406 if (status < 0)
413 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
414 if (status < 0)
416 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
417 if (status < 0)
419 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
420 if (status < 0)
422 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
423 if (status < 0)
427 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
428 if (status < 0)
430 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
431 if (status < 0)
436 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
437 if (status < 0)
442 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
443 if (status < 0)
448 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
449 if (status < 0)
451 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
452 if (status < 0)
454 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
455 if (status < 0)
459 return status;
464 int status = 0;
468 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
469 if (status < 0)
473 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
474 if (status < 0)
476 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
477 if (status < 0)
481 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
482 if (status < 0)
486 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
487 if (status < 0)
490 return status;
525 int status;
529 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
530 if (status < 0) {
531 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
532 return status;
555 int status;
565 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
566 if (status < 0)
570 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
571 if (status < 0)
576 status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
577 if (status < 0)
594 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
595 if (status < 0)
600 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
601 if (status < 0)
608 status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
609 if (status < 0)
619 status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
620 if (status < 0)
622 status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
623 if (status < 0)
672 status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
673 if (status < 0)
675 status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
676 if (status < 0)
678 status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
679 if (status < 0)
681 status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
682 if (status < 0)
684 status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
685 if (status < 0)
695 return status;
700 int status = 0;
713 status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
714 if (status < 0)
723 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
724 if (status < 0)
727 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
728 if (status < 0)
734 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
735 if (status < 0)
741 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
742 if (status < 0)
748 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
749 if (status < 0)
765 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
766 if (status < 0)
769 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
770 if (status < 0)
776 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
777 if (status < 0)
782 status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
783 if (status < 0)
793 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
794 if (status < 0)
800 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
801 if (status < 0)
816 status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
817 if (status < 0)
820 status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
821 if (status < 0)
827 status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
828 if (status < 0)
834 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
835 if (status < 0)
841 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
842 if (status < 0)
847 return status;
852 int status = 0;
857 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
859 if (status >= 0) {
887 return status;
917 int i, status = 0;
942 status = WriteBlock(state, Address, BlockSize,
944 if (status < 0)
949 return status;
955 int status;
957 status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
958 if (status < 0)
959 return status;
964 status = -1;
967 status = Read16(state, HI_RA_RAM_SRV_CMD__A, NULL, 0);
968 } while (status != 0);
970 if (status >= 0)
971 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
972 return status;
977 int status = 0;
990 status = Write16(state, HI_RA_RAM_SRV_CMD__A,
993 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, NULL);
995 return status;
1008 int status;
1011 status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
1013 if (status == 0)
1014 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, NULL);
1017 return status;
1040 int status;
1052 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1053 if (status < 0)
1055 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1056 if (status < 0)
1058 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1059 if (status < 0)
1061 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1062 if (status < 0)
1064 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1065 if (status < 0)
1068 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1069 if (status < 0)
1074 if (status >= 0) {
1078 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1080 if (status < 0)
1087 return status;
1094 int status;
1098 status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1102 return status;
1127 int status = 0;
1136 status |= Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
1137 status |= Write16(state, CC_REG_PLL_MODE__A,
1140 status |= Write16(state, CC_REG_REF_DIVIDE__A,
1142 status |= Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL,
1144 status |= Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
1146 return status;
1151 int status = 0;
1154 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
1156 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
1158 if (!(status < 0))
1159 status = WriteTable(state, state->m_ResetECRAM);
1160 if (!(status < 0))
1161 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
1162 return status;
1169 int status;
1176 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1177 if (status < 0)
1181 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1182 if (status < 0)
1186 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1187 if (status < 0)
1191 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1192 if (status < 0)
1197 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
1198 if (status < 0)
1204 status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1205 if (status < 0)
1209 status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1210 if (status < 0)
1214 status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1215 if (status < 0)
1219 status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1220 if (status < 0)
1225 status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
1226 if (status < 0)
1230 return status;
1235 int status;
1238 status = WriteTable(state, state->m_InitFE_1);
1239 if (status < 0)
1243 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
1248 status = SetCfgPga(state, 0);
1250 status =
1256 if (status < 0)
1258 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
1259 if (status < 0)
1261 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
1262 if (status < 0)
1265 status = WriteTable(state, state->m_InitFE_2);
1266 if (status < 0)
1271 return status;
1288 int status = Read16(state, SC_RA_RAM_CMD__A, NULL, 0);
1289 if (status == 0)
1290 return status;
1297 int status = 0, ret;
1300 status = Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
1301 if (status < 0)
1302 return status;
1310 status = -1;
1313 return status;
1319 int ret, status = 0;
1326 status = -1;
1330 status |= Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1331 status |= Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1332 status |= Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1337 return status;
1343 int status;
1347 status = SC_WaitForReady(state);
1348 if (status < 0)
1350 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1351 if (status < 0)
1353 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1354 if (status < 0)
1356 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1357 if (status < 0)
1360 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
1361 if (status < 0)
1365 return status;
1371 int status = 0;
1375 status = SC_WaitForReady(state);
1376 if (status < 0)
1378 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1379 if (status < 0)
1381 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1382 if (status < 0)
1386 return status;
1392 int status;
1464 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
1465 if (status < 0)
1467 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
1468 if (status < 0)
1470 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
1471 if (status < 0)
1473 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
1474 if (status < 0)
1477 return status;
1482 int status = 0;
1486 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1487 if (status < 0)
1490 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1491 if (status < 0)
1519 status = -1;
1525 if (status < 0)
1526 return status;
1571 return status;
1576 int status;
1590 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
1591 if (status < 0)
1593 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
1594 if (status < 0)
1650 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
1651 if (status < 0)
1655 status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
1656 if (status < 0)
1662 return status;
1667 int status;
1675 status = DRX_GetLockStatus(state, &lock);
1676 if (status < 0)
1680 status = StopOC(state);
1681 if (status < 0)
1686 status = ConfigureMPEGOutput(state, 0);
1687 if (status < 0)
1692 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
1693 if (status < 0)
1696 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1697 if (status < 0)
1699 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1700 if (status < 0)
1704 status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1705 if (status < 0)
1707 status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1708 if (status < 0)
1710 status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1711 if (status < 0)
1713 status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1714 if (status < 0)
1716 status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1717 if (status < 0)
1719 status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1720 if (status < 0)
1722 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
1723 if (status < 0)
1728 return status;
1734 int status;
1738 status = -1;
1743 status = 0;
1748 status = -1;
1754 status = WriteTable(state, state->m_InitDiversityFront);
1757 status = WriteTable(state, state->m_InitDiversityEnd);
1763 status = WriteTable(state, state->m_DisableDiversity);
1768 if (!status)
1770 return status;
1776 int status = 0;
1781 status = WriteTable(state, state->m_StartDiversityFront);
1782 if (status < 0)
1785 status = WriteTable(state, state->m_StartDiversityEnd);
1786 if (status < 0)
1789 status = WriteTable(state, state->m_DiversityDelay8MHZ);
1790 if (status < 0)
1793 status = WriteTable(state, state->m_DiversityDelay6MHZ);
1794 if (status < 0)
1798 status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
1799 if (status < 0)
1807 status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
1808 if (status < 0)
1812 return status;
1857 int status = 0;
1860 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
1861 if (status < 0)
1867 status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
1868 if (status < 0)
1871 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
1872 if (status < 0)
1876 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
1877 if (status < 0)
1879 status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
1880 if (status < 0)
1885 return status;
1891 int status;
1921 status = ResetECOD(state);
1922 if (status < 0)
1925 status = InitSC(state);
1926 if (status < 0)
1929 status = InitFT(state);
1930 if (status < 0)
1932 status = InitCP(state);
1933 if (status < 0)
1935 status = InitCE(state);
1936 if (status < 0)
1938 status = InitEQ(state);
1939 if (status < 0)
1941 status = InitSC(state);
1942 if (status < 0)
1948 status = SetCfgIfAgc(state, &state->if_agc_cfg);
1949 if (status < 0)
1951 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
1952 if (status < 0)
1964 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
1965 if (status < 0)
1975 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
1976 if (status < 0)
2009 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
2010 if (status < 0)
2012 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
2013 if (status < 0)
2039 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
2040 if (status < 0)
2042 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
2043 if (status < 0)
2068 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
2069 if (status < 0)
2071 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
2072 if (status < 0)
2100 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
2101 if (status < 0)
2103 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
2104 if (status < 0)
2127 if (status < 0)
2137 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
2138 if (status < 0)
2140 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
2141 if (status < 0)
2143 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
2144 if (status < 0)
2146 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
2147 if (status < 0)
2149 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
2150 if (status < 0)
2153 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
2154 if (status < 0)
2156 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
2157 if (status < 0)
2159 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
2160 if (status < 0)
2162 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
2163 if (status < 0)
2170 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
2171 if (status < 0)
2173 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
2174 if (status < 0)
2176 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2177 if (status < 0)
2179 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
2180 if (status < 0)
2182 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2183 if (status < 0)
2186 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
2187 if (status < 0)
2189 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
2190 if (status < 0)
2192 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
2193 if (status < 0)
2195 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
2196 if (status < 0)
2204 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
2205 if (status < 0)
2207 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
2208 if (status < 0)
2210 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2211 if (status < 0)
2213 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
2214 if (status < 0)
2216 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2217 if (status < 0)
2220 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
2221 if (status < 0)
2223 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
2224 if (status < 0)
2226 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
2227 if (status < 0)
2229 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
2230 if (status < 0)
2236 if (status < 0)
2244 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
2248 status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
2256 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
2264 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
2269 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
2274 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
2279 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
2282 if (status < 0)
2301 status = Write16(state,
2308 status = Write16(state,
2315 status = Write16(state,
2319 status = -EINVAL;
2321 if (status < 0)
2324 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
2325 if (status < 0)
2330 status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
2331 if (status < 0)
2344 status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
2345 if (status < 0)
2349 status = SetCfgNoiseCalibration(state, &state->noise_cal);
2350 if (status < 0)
2355 status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
2356 if (status < 0)
2367 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
2368 if (status < 0)
2370 status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
2371 if (status < 0)
2381 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
2382 if (status < 0)
2384 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
2385 if (status < 0)
2396 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
2397 if (status < 0)
2401 status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
2402 if (status < 0)
2405 status = StartOC(state);
2406 if (status < 0)
2410 status = StartDiversity(state);
2411 if (status < 0)
2418 return status;
2576 int status = 0;
2587 status = SetDeviceTypeId(state);
2588 if (status < 0)
2593 status = WriteTable(state, state->m_HiI2cPatch);
2594 if (status < 0)
2601 status = Write16(state, 0x43012D, 0x047f, 0);
2602 if (status < 0)
2606 status = HI_ResetCommand(state);
2607 if (status < 0)
2610 status = StopAllProcessors(state);
2611 if (status < 0)
2613 status = InitCC(state);
2614 if (status < 0)
2643 status = InitHI(state);
2644 if (status < 0)
2646 status = InitAtomicRead(state);
2647 if (status < 0)
2650 status = EnableAndResetMB(state);
2651 if (status < 0)
2654 status = ResetCEFR(state);
2655 if (status < 0)
2659 status = DownloadMicrocode(state, fw, fw_size);
2660 if (status < 0)
2663 status = DownloadMicrocode(state, state->microcode, state->microcode_length);
2664 if (status < 0)
2677 status = InitFE(state);
2678 if (status < 0)
2680 status = InitFT(state);
2681 if (status < 0)
2683 status = InitCP(state);
2684 if (status < 0)
2686 status = InitCE(state);
2687 if (status < 0)
2689 status = InitEQ(state);
2690 if (status < 0)
2692 status = InitEC(state);
2693 if (status < 0)
2695 status = InitSC(state);
2696 if (status < 0)
2699 status = SetCfgIfAgc(state, &state->if_agc_cfg);
2700 if (status < 0)
2702 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
2703 if (status < 0)
2707 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2708 if (status < 0)
2710 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2711 if (status < 0)
2722 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
2723 if (status < 0)
2726 status = StopOC(state);
2727 if (status < 0)
2732 status = 0;
2734 return status;
2744 /* Get status again, in case we have MPEG lock now */
2769 static int drxd_read_status(struct dvb_frontend *fe, enum fe_status *status)
2775 *status = 0;
2779 *status |= FE_HAS_LOCK;
2782 *status |= FE_HAS_LOCK;
2785 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
2787 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;