Lines Matching defs:addr
534 u32 addr,
545 u32 addr,
549 u32 addr,
553 u32 addr,
558 u32 addr,
562 u32 addr,
1003 * @addr: Destination address of the data in this block
1010 u32 addr;
1279 #define DRXJ_ISAUDWRITE(addr) (((((addr)>>16)&1) == 1) ? true : false)
1284 * \fn bool is_handled_by_aud_tr_if( u32 addr )
1286 * \param addr
1293 bool is_handled_by_aud_tr_if(u32 addr)
1297 if ((DRXDAP_FASI_ADDR2BLOCK(addr) == 4) &&
1298 (DRXDAP_FASI_ADDR2BANK(addr) > 1) &&
1299 (DRXDAP_FASI_ADDR2BANK(addr) < 6)) {
1321 msg[0].addr = r_dev_addr->i2c_addr >> 1;
1329 msg[0].addr = w_dev_addr->i2c_addr >> 1;
1337 msg[0].addr = w_dev_addr->i2c_addr >> 1;
1341 msg[1].addr = r_dev_addr->i2c_addr >> 1;
1366 msg[0].addr = w_dev_addr->i2c_addr;
1370 msg[1].addr = r_dev_addr->i2c_addr;
1376 pr_debug("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n",
1393 * u32 addr, -- address of chip register/memory
1415 u32 addr,
1429 (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
1431 if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
1433 DRXDAP_FASI_LONG_FORMAT(addr)) ||
1452 addr &= ~DRXDAP_FASI_FLAGS;
1453 addr |= flags;
1457 if (DRXDAP_FASI_LONG_FORMAT(addr)) {
1460 buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
1461 buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
1462 buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
1463 buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
1469 buf[bufx++] = (u8) ((addr << 1) & 0xFF);
1471 (u8) (((addr >> 16) & 0x0F) |
1472 ((addr >> 18) & 0xF0));
1493 addr += (todo >> 1);
1505 * u32 addr, -- address of chip register/memory
1520 u32 addr,
1529 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
1538 * u32 addr, -- address of chip register/memory
1553 u32 addr,
1562 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags);
1573 * u32 addr, -- address of chip register/memory
1592 u32 addr,
1607 (DRXDAP_FASI_LONG_FORMAT(addr) ? 4 : 2);
1609 if ((DRXDAP_FASI_OFFSET_TOO_LARGE(addr)) ||
1611 DRXDAP_FASI_LONG_FORMAT(addr)) ||
1629 addr &= ~DRXDAP_FASI_FLAGS;
1630 addr |= flags;
1633 if (DRXDAP_FASI_LONG_FORMAT(addr)) {
1636 buf[bufx++] = (u8) (((addr << 1) & 0xFF) | 0x01);
1637 buf[bufx++] = (u8) ((addr >> 16) & 0xFF);
1638 buf[bufx++] = (u8) ((addr >> 24) & 0xFF);
1639 buf[bufx++] = (u8) ((addr >> 7) & 0xFF);
1645 buf[bufx++] = (u8) ((addr << 1) & 0xFF);
1647 (u8) (((addr >> 16) & 0x0F) |
1648 ((addr >> 18) & 0xF0));
1656 sequense will be visible: (1) write address {i2c addr,
1657 4 bytes chip address} (2) write data {i2c addr, 4 bytes data }
1702 addr += (todo >> 1);
1712 * u32 addr, -- address of chip register/memory
1726 u32 addr,
1734 return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
1785 * u32 addr, -- address of chip register/memory
1799 u32 addr,
1809 return drxdap_fasi_write_block(dev_addr, addr, sizeof(data), buf, flags);
1897 * \param addr
1907 u32 addr, u16 *data)
1916 if (DRXDAP_FASI_ADDR2BANK(addr) == 3) {
1922 addr &= (~write_bit);
1929 addr,
1947 } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=3 ) */
1982 u32 addr,
1991 if (is_handled_by_aud_tr_if(addr))
1992 stat = drxj_dap_read_aud_reg16(dev_addr, addr, data);
1994 stat = drxdap_fasi_read_reg16(dev_addr, addr, data, flags);
2004 * \param addr
2014 u32 addr, u16 data)
2019 if (DRXDAP_FASI_ADDR2BANK(addr) == 2) {
2029 addr |= write_bit;
2034 addr,
2052 } /* if ( DRXDAP_FASI_ADDR2BANK(addr)!=2 ) */
2060 u32 addr,
2069 if (is_handled_by_aud_tr_if(addr))
2070 stat = drxj_dap_write_aud_reg16(dev_addr, addr, data);
2073 addr, data, flags);
2093 * \param addr destination/source address
2103 u32 addr,
2129 hi_cmd.param4 = (u16) ((DRXDAP_FASI_ADDR2BLOCK(addr) << 6) +
2130 DRXDAP_FASI_ADDR2BANK(addr));
2131 hi_cmd.param5 = (u16) DRXDAP_FASI_ADDR2OFFSET(addr);
2181 u32 addr,
2191 rc = drxj_dap_atomic_read_write_block(dev_addr, addr,
4132 * \param addr destination/source address
4142 int drxj_dap_scu_atomic_read_write_block(struct i2c_device_addr *dev_addr, u32 addr, u16 datasize, /* max 30 bytes because the limit of SCU parameter */
4154 set_param_parameters[1] = (u16) ADDR_AT_SCU_SPACE(addr);
4206 u32 addr,
4216 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true);
4234 u32 addr,
4243 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, false);
11667 block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data + count));
11676 pr_debug("%u: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n",
11677 count, block_hdr.addr, block_hdr.size, block_hdr.flags,
11681 u8 *auxblk = ((void *)mc_data) + block_hdr.addr;
11684 if (block_hdr.addr + sizeof(u16) > size)
11691 if (block_hdr.addr + 2 * sizeof(u16) + 2 * sizeof (u32) > size)
11811 block_hdr.addr = be32_to_cpu(*(__be32 *)(mc_data));
11820 pr_debug("%zd: addr %u, size %u, flags 0x%04x, CRC 0x%04x\n",
11821 (mc_data - mc_data_init), block_hdr.addr,
11847 block_hdr.addr,
11861 u32 curr_addr = block_hdr.addr;