Lines Matching defs:dib0090_write_reg
232 static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val)
323 dib0090_write_reg(state, r++, *b++);
515 dib0090_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL);
519 dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */
521 dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (0 << 4) | 0);
523 dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8)
526 dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8)
538 dib0090_write_reg(state, 0x21, PllCfg);
542 dib0090_write_reg(state, 0x21, PllCfg);
546 dib0090_write_reg(state, 0x21, PllCfg);
550 dib0090_write_reg(state, 0x21, PllCfg);
567 dib0090_write_reg(state, 0x21, PllCfg);
572 dib0090_write_reg(state, 0x21, PllCfg);
656 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
672 dib0090_write_reg(state, 0x04, 0);
674 dib0090_write_reg(state, 0x04, 1);
1015 dib0090_write_reg(state, gain_reg_addr[i], v);
1035 dib0090_write_reg(state, 0x2a, 0xffff);
1055 dib0090_write_reg(state, 0x33, 0xffff);
1122 dib0090_write_reg(state, 0x32, (en_pwm_rf_mux << 12) | (en_pwm_rf_mux << 11));
1126 dib0090_write_reg(state, 0x04, 3);
1128 dib0090_write_reg(state, 0x04, 1);
1129 dib0090_write_reg(state, 0x39, (1 << 10)); /* 0 gain by default */
1138 dib0090_write_reg(state, 0x04, DC_servo_cutoff);
1162 dib0090_write_reg(state, 0x04, 0x0);
1190 dib0090_write_reg(state, 0x32, 0);
1191 dib0090_write_reg(state, 0x39, 0);
1280 dib0090_write_reg(state, 0x02, (1 << 15) | (15 << 11) | (31 << 6) | (63)); /* cap value = 63 : narrow BB filter : Fc = 1.8MHz */
1281 dib0090_write_reg(state, 0x04, 0x0);
1285 dib0090_write_reg(state, 0x02, (1 << 15) | (3 << 11) | (6 << 6) | (32));
1286 dib0090_write_reg(state, 0x04, 0x01); /*0 = 1KHz ; 1 = 150Hz ; 2 = 50Hz ; 3 = 50KHz ; 4 = servo fast */
1352 dib0090_write_reg(state, 0x10, state->wbdmux);
1378 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xfff8)
1389 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x7fff)
1487 dib0090_write_reg(state, r, pgm_read_word(n++));
1513 dib0090_write_reg(state, 0x22, 0x10);
1539 dib0090_write_reg(state, 0x13, (h << 10));
1541 dib0090_write_reg(state, 0x2, e2); /* Load the BB_2 */
1560 dib0090_write_reg(state, 0x1b, (EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL));
1562 dib0090_write_reg(state, 0x1b, (EN_DIGCLK | EN_PLL | EN_CRYSTAL));
1568 dib0090_write_reg(state, 0x18, 0x2910); /* charge pump current = 0 */
1579 dib0090_write_reg(state, 0x14,
1582 dib0090_write_reg(state, 0x14, 1);
1584 dib0090_write_reg(state, 0x14, 2);
1601 dib0090_write_reg(state, 0x1f, 0x7);
1609 dib0090_write_reg(state, 0x1f, 0x4);
1667 dib0090_write_reg(state, state->dc->addr, *val);
1685 dib0090_write_reg(state, 0x24, reg);
1688 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x7 << 3) | 0x3);
1689 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));
1700 dib0090_write_reg(state, 0x01, state->dc->bb1);
1701 dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7));
1764 dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008);
1765 dib0090_write_reg(state, 0x1f, 0x7);
1801 dib0090_write_reg(state, 0x10, 0x1b81 | (1 << 10) | (wbd_gain << 13) | (1 << 3));
1803 dib0090_write_reg(state, 0x24, ((EN_UHF & 0x0fff) | (1 << 1)));
1837 dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */
1839 dib0090_write_reg(state, 0x03, 0x6008); /* = 0x6008 : vcm3_trim = 1 ; filter2_gm1_trim = 8 ; filter2_cutoff_freq = 0 */
1840 dib0090_write_reg(state, 0x04, 0x1); /* 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fast */
1842 dib0090_write_reg(state, 0x05, 0x9bcf); /* attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 1 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 15 */
1844 dib0090_write_reg(state, 0x02, (5 << 11) | (8 << 6) | (22 & 0x3f)); /* 22 = cap_value */
1845 dib0090_write_reg(state, 0x05, 0xabcd); /* = 0xabcd : attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 2 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 13 */
2067 dib0090_write_reg(state, 0x09, (dib0090_read_reg(state, 0x09) & 0x8000)
2069 dib0090_write_reg(state, 0x0b, (dib0090_read_reg(state, 0x0b) & 0xf83f)
2091 dib0090_write_reg(state, 0x10, 0x2B1);
2092 dib0090_write_reg(state, 0x1e, 0x0032);
2114 dib0090_write_reg(state, 0x40, (3 << 7) | (ratio << 2) | (1 << 1) | 1);
2119 dib0090_write_reg(state, 0x18, lo4 | state->captrim);
2128 dib0090_write_reg(state, 0x40, 0x18c | (0 << 1) | 0);
2169 dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim);
2189 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x8 << 3));
2192 dib0090_write_reg(state, 0x13, state->bias | (0x3 << 8));
2200 dib0090_write_reg(state, 0x13, (state->bias & ~(0x3 << 8)) | (0x2 << 8));
2214 dib0090_write_reg(state, 0x13, state->bias);
2215 dib0090_write_reg(state, 0x10, state->wbdmux); /* write back original WBDMUX */
2220 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
2253 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));
2257 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
2276 dib0090_write_reg(state, 0x39, tmp & ~(1 << 10));
2363 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim));
2432 dib0090_write_reg(state, 0x15, (u16) FBDiv);
2434 dib0090_write_reg(state, 0x16, (Den << 8) | state->config->fref_clock_ratio);
2436 dib0090_write_reg(state, 0x16, (Den << 8) | 1);
2437 dib0090_write_reg(state, 0x17, (u16) Rest);
2438 dib0090_write_reg(state, 0x19, lo5);
2439 dib0090_write_reg(state, 0x1c, lo6);
2445 dib0090_write_reg(state, 0x24, lo6 | EN_LO | state->config->use_pwm_agc * EN_CRYSTAL);
2462 dib0090_write_reg(state, 0x1e, 0x07ff);
2480 dib0090_write_reg(state, 0x10, state->wbdmux);
2484 dib0090_write_reg(state, 0x09, tune->lna_bias);
2485 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->lna_tune << 6) | (tune->switch_trim));
2487 dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | tune->lna_bias);
2489 dib0090_write_reg(state, 0x0c, tune->v2i);
2490 dib0090_write_reg(state, 0x0d, tune->mix);
2491 dib0090_write_reg(state, 0x0e, tune->load);