Lines Matching refs:au8522_writereg
178 au8522_writereg(state, AU8522_TVDEC_SHARPNESSREG009H, 0x07);
179 au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH, 0xed);
180 au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH, 0x79);
181 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH, 0x80);
182 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH, 0x80);
183 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH, 0x00);
184 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH, 0x00);
187 au8522_writereg(state, AU8522_TVDEC_INT_MASK_REG010H, 0x00);
190 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x04);
192 au8522_writereg(state, AU8522_VIDEO_MODE_REG011H, 0x00);
194 au8522_writereg(state, AU8522_TVDEC_PGA_REG012H,
196 au8522_writereg(state, AU8522_TVDEC_COMB_MODE_REG015H,
198 au8522_writereg(state, AU8522_TVDED_DBG_MODE_REG060H,
202 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
206 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
210 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL1_REG061H,
214 au8522_writereg(state, AU8522_TVDEC_FORMAT_CTRL2_REG062H,
217 au8522_writereg(state, AU8522_TVDEC_VCR_DET_LLIM_REG063H,
219 au8522_writereg(state, AU8522_TVDEC_VCR_DET_HLIM_REG064H,
221 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR1_REG065H,
223 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR2_REG066H,
225 au8522_writereg(state, AU8522_TVDEC_COMB_VDIF_THR3_REG067H,
227 au8522_writereg(state, AU8522_TVDEC_COMB_NOTCH_THR_REG068H,
229 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR1_REG069H,
231 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR2_REG06AH,
233 au8522_writereg(state, AU8522_TVDEC_COMB_HDIF_THR3_REG06BH,
236 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
238 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
241 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH,
243 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH,
246 au8522_writereg(state, AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH,
248 au8522_writereg(state, AU8522_TVDEC_UV_SEP_THR_REG06FH,
250 au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H,
252 au8522_writereg(state, AU8522_REG071H, AU8522_REG071H_CVBS);
253 au8522_writereg(state, AU8522_REG072H, AU8522_REG072H_CVBS);
254 au8522_writereg(state, AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H,
256 au8522_writereg(state, AU8522_REG074H, AU8522_REG074H_CVBS);
257 au8522_writereg(state, AU8522_REG075H, AU8522_REG075H_CVBS);
258 au8522_writereg(state, AU8522_TVDEC_DCAGC_CTRL_REG077H,
260 au8522_writereg(state, AU8522_TVDEC_PIC_START_ADJ_REG078H,
262 au8522_writereg(state, AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H,
264 au8522_writereg(state, AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH,
266 au8522_writereg(state, AU8522_TVDEC_INTRP_CTRL_REG07BH,
268 au8522_writereg(state, AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H,
270 au8522_writereg(state, AU8522_TOREGAAGC_REG0E5H,
272 au8522_writereg(state, AU8522_REG016H, AU8522_REG016H_CVBS);
283 au8522_writereg(state, filter_coef[i].reg_name,
289 au8522_writereg(state, AU8522_REG42EH, 0x87);
290 au8522_writereg(state, AU8522_REG42FH, 0xa2);
291 au8522_writereg(state, AU8522_REG430H, 0xbf);
292 au8522_writereg(state, AU8522_REG431H, 0xcb);
293 au8522_writereg(state, AU8522_REG432H, 0xa1);
294 au8522_writereg(state, AU8522_REG433H, 0x41);
295 au8522_writereg(state, AU8522_REG434H, 0x88);
296 au8522_writereg(state, AU8522_REG435H, 0xc2);
297 au8522_writereg(state, AU8522_REG436H, 0x3c);
303 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
307 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
310 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
312 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
316 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
324 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
329 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
332 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x0e);
335 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x10);
338 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
342 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
349 au8522_writereg(state, AU8522_MODULE_CLOCK_CONTROL_REG0A3H,
353 au8522_writereg(state, AU8522_INPUT_CONTROL_REG081H, input_mode);
356 au8522_writereg(state, AU8522_PGA_CONTROL_REG082H, 0x00);
359 au8522_writereg(state, AU8522_CLAMPING_CONTROL_REG083H, 0x00);
363 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
371 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x00);
372 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x00);
373 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0x00);
375 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x04);
376 au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0x02);
378 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
405 au8522_writereg(state, lpfilter_coef[i].reg_name,
410 au8522_writereg(state, AU8522_AUDIO_VOLUME_L_REG0F2H, 0x7F);
411 au8522_writereg(state, AU8522_AUDIO_VOLUME_R_REG0F3H, 0x7F);
412 au8522_writereg(state, AU8522_AUDIO_VOLUME_REG0F4H, 0xff);
415 au8522_writereg(state, AU8522_REG0F9H, AU8522_REG0F9H_AUDIO);
418 au8522_writereg(state, AU8522_AUDIO_MODE_REG0F1H, 0x82);
422 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H, 0x9d);
425 au8522_writereg(state, AU8522_AUDIOFREQ_REG606H, 0x03);
428 au8522_writereg(state, AU8522_I2S_CTRL_2_REG112H, 0xc2);
431 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H, 0x09);
443 au8522_writereg(state, AU8522_TVDEC_BRIGHTNESS_REG00AH,
447 au8522_writereg(state, AU8522_TVDEC_CONTRAST_REG00BH,
451 au8522_writereg(state, AU8522_TVDEC_SATURATION_CB_REG00CH,
453 au8522_writereg(state, AU8522_TVDEC_SATURATION_CR_REG00DH,
457 au8522_writereg(state, AU8522_TVDEC_HUE_H_REG00EH,
459 au8522_writereg(state, AU8522_TVDEC_HUE_L_REG00FH,
486 au8522_writereg(state, reg->reg, reg->val & 0xff);
495 au8522_writereg(state, 0xa4, 1 << 5);
542 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
553 au8522_writereg(state, AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H,
755 au8522_writereg(state, 0x106, 1);