Lines Matching defs:hsp
17 #include <dt-bindings/mailbox/tegra186-hsp.h>
64 struct tegra_hsp *hsp;
126 static inline u32 tegra_hsp_readl(struct tegra_hsp *hsp, unsigned int offset)
128 return readl(hsp->regs + offset);
131 static inline void tegra_hsp_writel(struct tegra_hsp *hsp, u32 value,
134 writel(value, hsp->regs + offset);
159 __tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
163 list_for_each_entry(entry, &hsp->doorbells, list)
171 tegra_hsp_doorbell_get(struct tegra_hsp *hsp, unsigned int master)
176 spin_lock_irqsave(&hsp->lock, flags);
177 db = __tegra_hsp_doorbell_get(hsp, master);
178 spin_unlock_irqrestore(&hsp->lock, flags);
185 struct tegra_hsp *hsp = data;
189 db = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
196 spin_lock(&hsp->lock);
198 for_each_set_bit(master, &value, hsp->mbox_db.num_chans) {
201 db = __tegra_hsp_doorbell_get(hsp, master);
217 spin_unlock(&hsp->lock);
224 struct tegra_hsp *hsp = data;
228 status = tegra_hsp_readl(hsp, HSP_INT_IR) & hsp->mask;
233 for_each_set_bit(bit, &mask, hsp->num_sm) {
234 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
244 spin_lock(&hsp->lock);
246 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
247 tegra_hsp_writel(hsp, hsp->mask,
248 HSP_INT_IE(hsp->shared_irq));
250 spin_unlock(&hsp->lock);
259 for_each_set_bit(bit, &mask, hsp->num_sm) {
260 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[bit];
270 tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name,
277 db = devm_kzalloc(hsp->dev, sizeof(*db), GFP_KERNEL);
281 offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K;
282 offset += index * hsp->soc->reg_stride;
284 db->channel.regs = hsp->regs + offset;
285 db->channel.hsp = hsp;
287 db->name = devm_kstrdup_const(hsp->dev, name, GFP_KERNEL);
291 spin_lock_irqsave(&hsp->lock, flags);
292 list_add_tail(&db->list, &hsp->doorbells);
293 spin_unlock_irqrestore(&hsp->lock, flags);
310 struct tegra_hsp *hsp = db->channel.hsp;
322 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
334 spin_lock_irqsave(&hsp->lock, flags);
340 spin_unlock_irqrestore(&hsp->lock, flags);
348 struct tegra_hsp *hsp = db->channel.hsp;
353 ccplex = tegra_hsp_doorbell_get(hsp, TEGRA_HSP_DB_MASTER_CCPLEX);
357 spin_lock_irqsave(&hsp->lock, flags);
363 spin_unlock_irqrestore(&hsp->lock, flags);
456 struct tegra_hsp *hsp = mb->channel.hsp;
465 spin_lock_irqsave(&hsp->lock, flags);
467 hsp->mask |= BIT(HSP_INT_EMPTY_SHIFT + mb->index);
468 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
470 spin_unlock_irqrestore(&hsp->lock, flags);
506 struct tegra_hsp *hsp = mb->channel.hsp;
522 spin_lock_irqsave(&hsp->lock, flags);
525 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
527 hsp->mask |= BIT(HSP_INT_FULL_SHIFT + mb->index);
529 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
531 spin_unlock_irqrestore(&hsp->lock, flags);
533 if (hsp->soc->has_per_mb_ie) {
549 struct tegra_hsp *hsp = mb->channel.hsp;
552 if (hsp->soc->has_per_mb_ie) {
561 spin_lock_irqsave(&hsp->lock, flags);
564 hsp->mask &= ~BIT(HSP_INT_EMPTY_SHIFT + mb->index);
566 hsp->mask &= ~BIT(HSP_INT_FULL_SHIFT + mb->index);
568 tegra_hsp_writel(hsp, hsp->mask, HSP_INT_IE(hsp->shared_irq));
570 spin_unlock_irqrestore(&hsp->lock, flags);
583 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_db);
591 if (type != TEGRA_HSP_MBOX_TYPE_DB || !hsp->doorbell_irq)
594 db = tegra_hsp_doorbell_get(hsp, master);
601 spin_lock_irqsave(&hsp->lock, flags);
614 spin_unlock_irqrestore(&hsp->lock, flags);
622 struct tegra_hsp *hsp = container_of(mbox, struct tegra_hsp, mbox_sm);
629 !hsp->shared_irqs || index >= hsp->num_sm)
632 mb = &hsp->mailboxes[index];
635 if (!hsp->soc->has_128_bit_mb)
651 static int tegra_hsp_add_doorbells(struct tegra_hsp *hsp)
653 const struct tegra_hsp_db_map *map = hsp->soc->map;
657 channel = tegra_hsp_doorbell_create(hsp, map->name,
668 static int tegra_hsp_add_mailboxes(struct tegra_hsp *hsp, struct device *dev)
672 hsp->mailboxes = devm_kcalloc(dev, hsp->num_sm, sizeof(*hsp->mailboxes),
674 if (!hsp->mailboxes)
677 for (i = 0; i < hsp->num_sm; i++) {
678 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
682 mb->channel.hsp = hsp;
683 mb->channel.regs = hsp->regs + SZ_64K + i * SZ_32K;
684 mb->channel.chan = &hsp->mbox_sm.chans[i];
691 static int tegra_hsp_request_shared_irq(struct tegra_hsp *hsp)
696 for (i = 0; i < hsp->num_si; i++) {
697 irq = hsp->shared_irqs[i];
701 err = devm_request_irq(hsp->dev, irq, tegra_hsp_shared_irq, 0,
702 dev_name(hsp->dev), hsp);
704 dev_err(hsp->dev, "failed to request interrupt: %d\n",
709 hsp->shared_irq = i;
712 tegra_hsp_writel(hsp, 0, HSP_INT_IE(hsp->shared_irq));
714 dev_dbg(hsp->dev, "interrupt requested: %u\n", irq);
719 if (i == hsp->num_si) {
720 dev_err(hsp->dev, "failed to find available interrupt\n");
729 struct tegra_hsp *hsp;
734 hsp = devm_kzalloc(&pdev->dev, sizeof(*hsp), GFP_KERNEL);
735 if (!hsp)
738 hsp->dev = &pdev->dev;
739 hsp->soc = of_device_get_match_data(&pdev->dev);
740 INIT_LIST_HEAD(&hsp->doorbells);
741 spin_lock_init(&hsp->lock);
743 hsp->regs = devm_platform_ioremap_resource(pdev, 0);
744 if (IS_ERR(hsp->regs))
745 return PTR_ERR(hsp->regs);
747 value = tegra_hsp_readl(hsp, HSP_INT_DIMENSIONING);
748 hsp->num_sm = (value >> HSP_nSM_SHIFT) & HSP_nINT_MASK;
749 hsp->num_ss = (value >> HSP_nSS_SHIFT) & HSP_nINT_MASK;
750 hsp->num_as = (value >> HSP_nAS_SHIFT) & HSP_nINT_MASK;
751 hsp->num_db = (value >> HSP_nDB_SHIFT) & HSP_nINT_MASK;
752 hsp->num_si = (value >> HSP_nSI_SHIFT) & HSP_nINT_MASK;
756 hsp->doorbell_irq = err;
758 if (hsp->num_si > 0) {
761 hsp->shared_irqs = devm_kcalloc(&pdev->dev, hsp->num_si,
762 sizeof(*hsp->shared_irqs),
764 if (!hsp->shared_irqs)
767 for (i = 0; i < hsp->num_si; i++) {
776 hsp->shared_irqs[i] = err;
784 devm_kfree(&pdev->dev, hsp->shared_irqs);
785 hsp->shared_irqs = NULL;
790 hsp->mbox_db.of_xlate = tegra_hsp_db_xlate;
791 hsp->mbox_db.num_chans = 32;
792 hsp->mbox_db.dev = &pdev->dev;
793 hsp->mbox_db.ops = &tegra_hsp_db_ops;
795 hsp->mbox_db.chans = devm_kcalloc(&pdev->dev, hsp->mbox_db.num_chans,
796 sizeof(*hsp->mbox_db.chans),
798 if (!hsp->mbox_db.chans)
801 if (hsp->doorbell_irq) {
802 err = tegra_hsp_add_doorbells(hsp);
810 err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_db);
818 hsp->mbox_sm.of_xlate = tegra_hsp_sm_xlate;
819 hsp->mbox_sm.num_chans = hsp->num_sm;
820 hsp->mbox_sm.dev = &pdev->dev;
821 hsp->mbox_sm.ops = &tegra_hsp_sm_ops;
823 hsp->mbox_sm.chans = devm_kcalloc(&pdev->dev, hsp->mbox_sm.num_chans,
824 sizeof(*hsp->mbox_sm.chans),
826 if (!hsp->mbox_sm.chans)
829 if (hsp->shared_irqs) {
830 err = tegra_hsp_add_mailboxes(hsp, &pdev->dev);
838 err = devm_mbox_controller_register(&pdev->dev, &hsp->mbox_sm);
845 platform_set_drvdata(pdev, hsp);
847 if (hsp->doorbell_irq) {
848 err = devm_request_irq(&pdev->dev, hsp->doorbell_irq,
850 dev_name(&pdev->dev), hsp);
854 hsp->doorbell_irq, err);
859 if (hsp->shared_irqs) {
860 err = tegra_hsp_request_shared_irq(hsp);
865 lockdep_register_key(&hsp->lock_key);
866 lockdep_set_class(&hsp->lock, &hsp->lock_key);
873 struct tegra_hsp *hsp = platform_get_drvdata(pdev);
875 lockdep_unregister_key(&hsp->lock_key);
882 struct tegra_hsp *hsp = dev_get_drvdata(dev);
886 list_for_each_entry(db, &hsp->doorbells, list) {
891 if (hsp->mailboxes) {
892 for (i = 0; i < hsp->num_sm; i++) {
893 struct tegra_hsp_mailbox *mb = &hsp->mailboxes[i];
942 { .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc },
943 { .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc },
944 { .compatible = "nvidia,tegra234-hsp", .data = &tegra234_hsp_soc },
945 { .compatible = "nvidia,tegra264-hsp", .data = &tegra264_hsp_soc },
951 .name = "tegra-hsp",