Lines Matching defs:ipcc
84 struct stm32_ipcc *ipcc = data;
85 struct device *dev = ipcc->controller.dev;
91 proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
92 tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
93 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
98 for (chan = 0; chan < ipcc->n_chans; chan++) {
104 mbox_chan_received_data(&ipcc->controller.chans[chan], NULL);
106 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,
117 struct stm32_ipcc *ipcc = data;
118 struct device *dev = ipcc->controller.dev;
122 tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR);
123 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
128 for (chan = 0; chan < ipcc->n_chans ; chan++) {
135 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
138 mbox_chan_txdone(&ipcc->controller.chans[chan], 0);
149 struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
152 dev_dbg(ipcc->controller.dev, "%s: chan:%lu\n", __func__, chan);
155 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR,
159 stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
168 struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
172 ret = clk_prepare_enable(ipcc->clk);
174 dev_err(ipcc->controller.dev, "can not enable the clock\n");
179 stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
188 struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
192 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
195 clk_disable_unprepare(ipcc->clk);
208 struct stm32_ipcc *ipcc;
220 ipcc = devm_kzalloc(dev, sizeof(*ipcc), GFP_KERNEL);
221 if (!ipcc)
224 spin_lock_init(&ipcc->lock);
227 if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) {
232 if (ipcc->proc_id >= STM32_MAX_PROCS) {
233 dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
238 ipcc->reg_base = devm_platform_ioremap_resource(pdev, 0);
239 if (IS_ERR(ipcc->reg_base))
240 return PTR_ERR(ipcc->reg_base);
242 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;
245 ipcc->clk = devm_clk_get(dev, NULL);
246 if (IS_ERR(ipcc->clk))
247 return PTR_ERR(ipcc->clk);
249 ret = clk_prepare_enable(ipcc->clk);
257 ipcc->irqs[i] = platform_get_irq_byname(pdev, irq_name[i]);
258 if (ipcc->irqs[i] < 0) {
259 ret = ipcc->irqs[i];
263 ret = devm_request_threaded_irq(dev, ipcc->irqs[i], NULL,
265 dev_name(dev), ipcc);
273 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR,
275 stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XCR,
282 ret = dev_pm_set_wake_irq(dev, ipcc->irqs[IPCC_IRQ_RX]);
290 ipcc->n_chans = readl_relaxed(ipcc->reg_base + IPCC_HWCFGR);
291 ipcc->n_chans &= IPCFGR_CHAN_MASK;
293 ipcc->controller.dev = dev;
294 ipcc->controller.txdone_irq = true;
295 ipcc->controller.ops = &stm32_ipcc_ops;
296 ipcc->controller.num_chans = ipcc->n_chans;
297 ipcc->controller.chans = devm_kcalloc(dev, ipcc->controller.num_chans,
298 sizeof(*ipcc->controller.chans),
300 if (!ipcc->controller.chans) {
305 for (i = 0; i < ipcc->controller.num_chans; i++)
306 ipcc->controller.chans[i].con_priv = (void *)i;
308 ret = devm_mbox_controller_register(dev, &ipcc->controller);
312 platform_set_drvdata(pdev, ipcc);
314 ip_ver = readl_relaxed(ipcc->reg_base + IPCC_VER);
316 dev_info(dev, "ipcc rev:%ld.%ld enabled, %d chans, proc %d\n",
319 ipcc->controller.num_chans, ipcc->proc_id);
321 clk_disable_unprepare(ipcc->clk);
330 clk_disable_unprepare(ipcc->clk);
349 struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
351 ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
352 ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR);
359 struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
361 writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR);
362 writel_relaxed(ipcc->xcr, ipcc->reg_proc + IPCC_XCR);
372 { .compatible = "st,stm32mp1-ipcc" },
379 .name = "stm32-ipcc",