Lines Matching defs:SPRD_MBOX_IRQ_MSK
25 #define SPRD_MBOX_IRQ_MSK 0x1c
44 /* Bit and mask definition for inbox's SPRD_MBOX_IRQ_MSK register */
50 /* Bit and mask definition for outbox's SPRD_MBOX_IRQ_MSK register */
248 val = readl(priv->inbox_base + SPRD_MBOX_IRQ_MSK);
250 writel(val, priv->inbox_base + SPRD_MBOX_IRQ_MSK);
253 val = readl(priv->outbox_base + SPRD_MBOX_IRQ_MSK);
255 writel(val, priv->outbox_base + SPRD_MBOX_IRQ_MSK);
260 val = readl(priv->supp_base + SPRD_MBOX_IRQ_MSK);
262 writel(val, priv->supp_base + SPRD_MBOX_IRQ_MSK);
277 writel(SPRD_INBOX_FIFO_IRQ_MASK, priv->inbox_base + SPRD_MBOX_IRQ_MSK);
278 writel(SPRD_OUTBOX_FIFO_IRQ_MASK, priv->outbox_base + SPRD_MBOX_IRQ_MSK);
282 priv->supp_base + SPRD_MBOX_IRQ_MSK);