Lines Matching refs:dcfg
89 const struct imx_mu_dcfg *dcfg;
159 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
160 can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4);
169 imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4);
183 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
184 can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4);
193 *val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4);
205 val = imx_mu_read(priv, priv->dcfg->xCR[type]);
208 imx_mu_write(priv, val, priv->dcfg->xCR[type]);
222 imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4);
223 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
226 imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
242 dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4);
251 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
252 priv->dcfg->xSR[IMX_MU_GSR]);
265 if (priv->dcfg->type & IMX_MU_V2_S4) {
292 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
294 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR],
296 xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr),
302 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4);
305 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0);
324 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0));
325 *data++ = imx_mu_read(priv, priv->dcfg->xRR);
327 if (priv->dcfg->type & IMX_MU_V2_S4) {
341 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
342 xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0,
348 *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
351 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
387 imx_mu_write(priv, *arg++, priv->dcfg->xTR);
392 IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0);
398 priv->dcfg->xTR + (i % 4) * 4);
437 *data++ = imx_mu_read(priv, priv->dcfg->xRR);
457 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
458 priv->dcfg->xSR[IMX_MU_GSR]);
492 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]);
493 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]);
494 val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) &
495 (ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
498 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]);
499 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]);
500 val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) &
501 (ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
504 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]);
505 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
506 val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) &
507 (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
520 if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) &&
522 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
524 } else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) &&
526 priv->dcfg->rx(priv, cp);
527 } else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) &&
529 priv->dcfg->rxdb(priv, cp);
546 return priv->dcfg->tx(priv, cp, data);
568 if (!(priv->dcfg->type & IMX_MU_V2_IRQ))
579 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0);
582 imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0);
606 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx));
609 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx));
612 imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
615 imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0);
616 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr,
617 !(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5);
738 imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
741 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]);
742 imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]);
746 imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
752 int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS;
770 imx_mu_write(priv, 0, priv->dcfg->xCR[i]);
784 const struct imx_mu_dcfg *dcfg;
798 dcfg = of_device_get_match_data(dev);
799 if (!dcfg)
801 priv->dcfg = dcfg;
802 if (priv->dcfg->type & IMX_MU_V2_IRQ) {
818 if (priv->dcfg->type & IMX_MU_V2_S4)
843 priv->dcfg->init(priv);
986 priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]);
1007 if (!priv->clk && !imx_mu_read(priv, priv->dcfg->xCR[0])) {
1009 imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]);