Lines Matching refs:val
232 set_debug(const char *val, const struct kernel_param *kp)
237 ret = param_set_uint(val, kp);
268 u8 val;
271 val = inb((u32)hw->cfg.start + DIVA_PCI_CTRL);
272 if (!(val & DIVA_IRQ_BIT)) { /* for us or shared ? */
286 u8 val;
289 val = readb(hw->cfg.p);
290 if (!(val & PITA_INT0_STATUS)) { /* for us or shared ? */
305 u8 val;
308 val = inb((u32)hw->cfg.start + TIGER_AUX_STATUS);
309 if (val & TIGER_IRQ_BIT) { /* for us or shared ? */
323 u8 val;
326 val = inb((u32)hw->cfg.start + ELSA_IRQ_ADDR);
327 if (!(val & ELSA_IRQ_MASK)) {
341 u32 val;
344 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
345 if (!(val & NICCY_IRQ_BIT)) { /* for us or shared ? */
349 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
372 u8 val;
375 val = hw->ipac.read_reg(hw, IPAC_ISTA);
376 if (!(val & 0x3f)) {
390 u32 val;
408 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
409 val |= NICCY_IRQ_ENABLE;
410 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
434 u32 val;
452 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
453 val &= NICCY_IRQ_DISABLE;
454 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG);
485 u32 val;
543 val = inl((u32)hw->cfg.start + GAZEL_CNTRL);
544 val |= (GAZEL_RESET_9050 + GAZEL_RESET);
545 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
546 val &= ~(GAZEL_RESET_9050 + GAZEL_RESET);
548 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
555 val = inl((u32)hw->cfg.start + GAZEL_CNTRL);
556 val |= (GAZEL_RESET_9050 + GAZEL_RESET);
557 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);
558 val &= ~(GAZEL_RESET_9050 + GAZEL_RESET);
560 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL);