Lines Matching refs:gc
75 static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off,
78 irq_reg_writel(gc, val, off);
81 static inline u32 sunxi_sc_nmi_read(struct irq_chip_generic *gc, u32 off)
83 return irq_reg_readl(gc, off);
98 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
99 struct irq_chip_type *ct = gc->chip_types;
105 irq_gc_lock(gc);
122 irq_gc_unlock(gc);
131 for (i = 0; i < gc->num_ct; i++, ct++)
135 src_type_reg = sunxi_sc_nmi_read(gc, ctrl_off);
138 sunxi_sc_nmi_write(gc, ctrl_off, src_type_reg);
140 irq_gc_unlock(gc);
149 struct irq_chip_generic *gc;
176 gc = irq_get_domain_generic_chip(domain, 0);
177 gc->reg_base = of_io_request_and_map(node, 0, of_node_full_name(node));
178 if (IS_ERR(gc->reg_base)) {
180 ret = PTR_ERR(gc->reg_base);
184 gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
185 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
186 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
187 gc->chip_types[0].chip.irq_eoi = irq_gc_ack_set_bit;
188 gc->chip_types[0].chip.irq_set_type = sunxi_sc_nmi_set_type;
189 gc->chip_types[0].chip.flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED;
190 gc->chip_types[0].regs.ack = reg_offs->pend;
191 gc->chip_types[0].regs.mask = reg_offs->enable;
192 gc->chip_types[0].regs.type = reg_offs->ctrl;
194 gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
195 gc->chip_types[1].chip.name = gc->chip_types[0].chip.name;
196 gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit;
197 gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit;
198 gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit;
199 gc->chip_types[1].chip.irq_set_type = sunxi_sc_nmi_set_type;
200 gc->chip_types[1].regs.ack = reg_offs->pend;
201 gc->chip_types[1].regs.mask = reg_offs->enable;
202 gc->chip_types[1].regs.type = reg_offs->ctrl;
203 gc->chip_types[1].handler = handle_edge_irq;
206 sunxi_sc_nmi_write(gc, reg_offs->enable, 0);
209 sunxi_sc_nmi_write(gc, reg_offs->pend, SUNXI_NMI_IRQ_BIT);