Lines Matching refs:hwirq
81 static void sp_intc_assign_bit(u32 hwirq, void __iomem *base, bool value)
87 offset = (hwirq / 32) * 4;
93 mask |= BIT(hwirq % 32);
95 mask &= ~BIT(hwirq % 32);
102 u32 hwirq = d->hwirq;
104 if (unlikely(IS_GPIO_INT(hwirq) && TEST_STATE(hwirq, _IS_EDGE))) { // WORKAROUND
105 sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, !TEST_STATE(hwirq, _IS_LOW));
106 ASSIGN_STATE(hwirq, _IS_ACTIVE, true);
109 sp_intc_assign_bit(hwirq, REG_INTR_CLEAR, 1);
114 sp_intc_assign_bit(d->hwirq, REG_INTR_MASK, 0);
119 sp_intc_assign_bit(d->hwirq, REG_INTR_MASK, 1);
124 u32 hwirq = d->hwirq;
130 if (unlikely(IS_GPIO_INT(hwirq) && is_edge)) { // WORKAROUND
132 ASSIGN_STATE(hwirq, _IS_EDGE, is_edge);
133 ASSIGN_STATE(hwirq, _IS_LOW, is_low);
134 ASSIGN_STATE(hwirq, _IS_ACTIVE, false);
139 sp_intc_assign_bit(hwirq, REG_INTR_TYPE, is_edge);
140 sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, is_low);
171 int hwirq;
175 while ((hwirq = sp_intc_get_ext_irq(ext_num)) >= 0) {
176 if (unlikely(IS_GPIO_INT(hwirq) && TEST_STATE(hwirq, _IS_ACTIVE))) { // WORKAROUND
177 ASSIGN_STATE(hwirq, _IS_ACTIVE, false);
178 sp_intc_assign_bit(hwirq, REG_INTR_POLARITY, TEST_STATE(hwirq, _IS_LOW));
180 generic_handle_domain_irq(sp_intc.domain, hwirq);
196 unsigned int irq, irq_hw_number_t hwirq)