Lines Matching refs:hwirq
93 static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable)
95 u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32);
96 u32 hwirq_mask = 1 << (hwirq % 32);
104 static void plic_toggle(struct plic_handler *handler, int hwirq, int enable)
107 __plic_toggle(handler->enable_base, hwirq, enable);
119 plic_toggle(handler, d->hwirq, enable);
137 writel(1, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
144 writel(0, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
152 plic_toggle(handler, d->hwirq, 1);
153 writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
154 plic_toggle(handler, d->hwirq, 0);
156 writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
308 irq_hw_number_t hwirq)
312 irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data,
321 unsigned long *hwirq,
327 return irq_domain_translate_twocell(d, fwspec, hwirq, type);
329 return irq_domain_translate_onecell(d, fwspec, hwirq, type);
336 irq_hw_number_t hwirq;
340 ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type);
345 ret = plic_irqdomain_map(domain, virq + i, hwirq + i);
370 irq_hw_number_t hwirq;
376 while ((hwirq = readl(claim))) {
378 hwirq);
380 pr_warn_ratelimited("can't find mapping for hwirq %lu\n",
381 hwirq);
460 irq_hw_number_t hwirq;
480 for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
481 __plic_toggle(enable_base, hwirq, 0);
532 for (hwirq = 1; hwirq <= nr_irqs; hwirq++) {
533 plic_toggle(handler, hwirq, 0);
535 hwirq * PRIORITY_PER_ID);