Lines Matching refs:val
246 enum irqchip_irq_state which, bool val)
252 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
256 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
260 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
272 enum irqchip_irq_state which, bool *val)
276 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
280 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
284 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
439 u32 val = readl_relaxed(base + GIC_CPU_IDENT);
440 return (val & 0xff0fff) == 0x02043B;
533 u32 val = 0;
539 val = readl(cpu_base + GIC_CPU_CTRL);
540 val &= ~GICC_ENABLE;
541 writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
783 u32 val;
788 val = readl_relaxed(addr);
789 val &= ~GENMASK(shift + 7, shift);
790 val |= bval << shift;
791 writel_relaxed(val, addr);
967 u32 val, cur_target_mask, active_mask;
991 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
992 active_mask = val & cur_target_mask;
994 val &= ~active_mask;
995 val |= ror32(active_mask, ror_val);
996 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
1014 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
1015 if (!val)
1017 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
1019 if (val & 0xff)
1022 val >>= 8;