Lines Matching refs:gic
42 #include <linux/irqchip/arm-gic.h>
50 #include "irq-gic-common.h"
340 struct gic_chip_data *gic = &gic_data[0];
341 void __iomem *cpu_base = gic_data_cpu_base(gic);
373 generic_handle_domain_irq(gic->domain, irqnr);
403 struct gic_chip_data *gic = irq_data_get_irq_chip_data(d);
405 if (gic->domain->pm_dev)
406 seq_printf(p, gic->domain->pm_dev->of_node->name);
408 seq_printf(p, "GIC-%d", (int)(gic - &gic_data[0]));
418 static u8 gic_get_cpumask(struct gic_chip_data *gic)
420 void __iomem *base = gic_data_dist_base(gic);
443 static void gic_cpu_if_up(struct gic_chip_data *gic)
445 void __iomem *cpu_base = gic_data_cpu_base(gic);
450 if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key))
467 static void gic_dist_init(struct gic_chip_data *gic)
471 unsigned int gic_irqs = gic->gic_irqs;
472 void __iomem *base = gic_data_dist_base(gic);
479 cpumask = gic_get_cpumask(gic);
490 static int gic_cpu_init(struct gic_chip_data *gic)
492 void __iomem *dist_base = gic_data_dist_base(gic);
493 void __iomem *base = gic_data_cpu_base(gic);
502 if (gic == &gic_data[0]) {
510 cpu_mask = gic_get_cpumask(gic);
525 gic_cpu_if_up(gic);
553 void gic_dist_save(struct gic_chip_data *gic)
559 if (WARN_ON(!gic))
562 gic_irqs = gic->gic_irqs;
563 dist_base = gic_data_dist_base(gic);
569 gic->saved_spi_conf[i] =
573 gic->saved_spi_target[i] =
577 gic->saved_spi_enable[i] =
581 gic->saved_spi_active[i] =
592 void gic_dist_restore(struct gic_chip_data *gic)
598 if (WARN_ON(!gic))
601 gic_irqs = gic->gic_irqs;
602 dist_base = gic_data_dist_base(gic);
610 writel_relaxed(gic->saved_spi_conf[i],
618 writel_relaxed(gic->saved_spi_target[i],
624 writel_relaxed(gic->saved_spi_enable[i],
631 writel_relaxed(gic->saved_spi_active[i],
638 void gic_cpu_save(struct gic_chip_data *gic)
645 if (WARN_ON(!gic))
648 dist_base = gic_data_dist_base(gic);
649 cpu_base = gic_data_cpu_base(gic);
654 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
658 ptr = raw_cpu_ptr(gic->saved_ppi_active);
662 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
668 void gic_cpu_restore(struct gic_chip_data *gic)
675 if (WARN_ON(!gic))
678 dist_base = gic_data_dist_base(gic);
679 cpu_base = gic_data_cpu_base(gic);
684 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
691 ptr = raw_cpu_ptr(gic->saved_ppi_active);
698 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
707 gic_cpu_if_up(gic);
740 static int gic_pm_init(struct gic_chip_data *gic)
742 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
744 if (WARN_ON(!gic->saved_ppi_enable))
747 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
749 if (WARN_ON(!gic->saved_ppi_active))
752 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
754 if (WARN_ON(!gic->saved_ppi_conf))
757 if (gic == &gic_data[0])
763 free_percpu(gic->saved_ppi_active);
765 free_percpu(gic->saved_ppi_enable);
770 static int gic_pm_init(struct gic_chip_data *gic)
800 struct gic_chip_data *gic = irq_data_get_irq_chip_data(d);
803 if (unlikely(gic != &gic_data[0]))
868 "irqchip/arm/gic:starting",
1058 struct gic_chip_data *gic = d->host_data;
1063 gic == &gic_data[0]) ? &gic_chip_mode1 : &gic_chip;
1166 static int gic_init_bases(struct gic_chip_data *gic,
1171 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1175 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1176 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1177 if (WARN_ON(!gic->dist_base.percpu_base ||
1178 !gic->cpu_base.percpu_base)) {
1186 unsigned long offset = gic->percpu_offset * core_id;
1187 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) =
1188 gic->raw_dist_base + offset;
1189 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =
1190 gic->raw_cpu_base + offset;
1196 WARN(gic->percpu_offset,
1198 gic->percpu_offset);
1199 gic->dist_base.common_base = gic->raw_dist_base;
1200 gic->cpu_base.common_base = gic->raw_cpu_base;
1207 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1211 gic->gic_irqs = gic_irqs;
1213 gic->domain = irq_domain_create_linear(handle, gic_irqs,
1215 gic);
1216 if (WARN_ON(!gic->domain)) {
1221 gic_dist_init(gic);
1222 ret = gic_cpu_init(gic);
1226 ret = gic_pm_init(gic);
1233 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1234 free_percpu(gic->dist_base.percpu_base);
1235 free_percpu(gic->cpu_base.percpu_base);
1241 static int __init __gic_init_bases(struct gic_chip_data *gic,
1246 if (WARN_ON(!gic || gic->domain))
1249 if (gic == &gic_data[0]) {
1263 ret = gic_init_bases(gic, handle);
1264 if (gic == &gic_data[0])
1270 static void gic_teardown(struct gic_chip_data *gic)
1272 if (WARN_ON(!gic))
1275 if (gic->raw_dist_base)
1276 iounmap(gic->raw_dist_base);
1277 if (gic->raw_cpu_base)
1278 iounmap(gic->raw_cpu_base);
1392 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
1394 if (!gic || !node)
1397 gic->raw_dist_base = of_iomap(node, 0);
1398 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
1401 gic->raw_cpu_base = of_iomap(node, 1);
1402 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
1405 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
1406 gic->percpu_offset = 0;
1408 gic_enable_of_quirks(node, gic_quirks, gic);
1413 gic_teardown(gic);
1418 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1422 if (!dev || !dev->of_node || !gic || !irq)
1425 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);
1426 if (!*gic)
1429 ret = gic_of_setup(*gic, dev->of_node);
1433 ret = gic_init_bases(*gic, &dev->of_node->fwnode);
1435 gic_teardown(*gic);
1439 irq_domain_set_pm_device((*gic)->domain, dev);
1440 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);
1472 struct gic_chip_data *gic;
1481 gic = &gic_data[gic_cnt];
1483 ret = gic_of_setup(gic, node);
1491 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
1494 ret = __gic_init_bases(gic, &node->fwnode);
1496 gic_teardown(gic);
1516 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1517 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1518 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1519 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1520 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1521 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1641 struct gic_chip_data *gic = &gic_data[0];
1652 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1653 if (!gic->raw_cpu_base) {
1659 gic->raw_dist_base = ioremap(dist->base_address,
1661 if (!gic->raw_dist_base) {
1663 gic_teardown(gic);
1681 gic_teardown(gic);
1685 ret = __gic_init_bases(gic, gsi_domain_handle);
1689 gic_teardown(gic);