Lines Matching refs:base
12 * associated CPU. The base address of the CPU interface is usually
137 static inline void __iomem *__get_base(union gic_base *base)
140 return raw_cpu_read(*base->percpu_base);
142 return base->common_base;
296 void __iomem *base = gic_dist_base(d);
309 ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL);
420 void __iomem *base = gic_data_dist_base(gic);
424 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
437 static bool gic_check_gicv2(void __iomem *base)
439 u32 val = readl_relaxed(base + GIC_CPU_IDENT);
472 void __iomem *base = gic_data_dist_base(gic);
474 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
483 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
485 gic_dist_config(base, gic_irqs, NULL);
487 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
493 void __iomem *base = gic_data_cpu_base(gic);
524 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
1290 static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1304 if (!gic_check_gicv2(*base))
1323 iounmap(*base);
1324 *base = alt;
1341 iounmap(*base);
1342 *base = alt;
1350 if (!gic_check_gicv2(*base) ||
1351 !gic_check_gicv2(*base + 0xf000))
1355 * Move the base up by 60kB, so that we have a 8kB
1359 *base += 0xf000;
1361 pr_warn("GIC: Adjusting CPU interface base to %pa\n",
1644 /* Collect CPU base addresses */