Lines Matching refs:as
277 struct tegra_smmu_as *as;
282 as = kzalloc(sizeof(*as), GFP_KERNEL);
283 if (!as)
286 as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE;
288 as->pd = alloc_page(GFP_KERNEL | __GFP_DMA | __GFP_ZERO);
289 if (!as->pd) {
290 kfree(as);
294 as->count = kcalloc(SMMU_NUM_PDE, sizeof(u32), GFP_KERNEL);
295 if (!as->count) {
296 __free_page(as->pd);
297 kfree(as);
301 as->pts = kcalloc(SMMU_NUM_PDE, sizeof(*as->pts), GFP_KERNEL);
302 if (!as->pts) {
303 kfree(as->count);
304 __free_page(as->pd);
305 kfree(as);
309 spin_lock_init(&as->lock);
312 as->domain.geometry.aperture_start = 0;
313 as->domain.geometry.aperture_end = 0xffffffff;
314 as->domain.geometry.force_aperture = true;
316 return &as->domain;
321 struct tegra_smmu_as *as = to_smmu_as(domain);
325 WARN_ON_ONCE(as->use_count);
326 kfree(as->count);
327 kfree(as->pts);
328 kfree(as);
409 struct tegra_smmu_as *as)
416 if (as->use_count > 0) {
417 as->use_count++;
421 as->pd_dma = dma_map_page(smmu->dev, as->pd, 0, SMMU_SIZE_PD,
423 if (dma_mapping_error(smmu->dev, as->pd_dma)) {
429 if (!smmu_dma_addr_valid(smmu, as->pd_dma)) {
434 err = tegra_smmu_alloc_asid(smmu, &as->id);
438 smmu_flush_ptc(smmu, as->pd_dma, 0);
439 smmu_flush_tlb_asid(smmu, as->id);
441 smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID);
442 value = SMMU_PTB_DATA_VALUE(as->pd_dma, as->attr);
446 as->smmu = smmu;
447 as->use_count++;
454 dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE);
462 struct tegra_smmu_as *as)
466 if (--as->use_count > 0) {
471 tegra_smmu_free_asid(smmu, as->id);
473 dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE);
475 as->smmu = NULL;
485 struct tegra_smmu_as *as = to_smmu_as(domain);
493 err = tegra_smmu_as_prepare(smmu, as);
497 tegra_smmu_enable(smmu, fwspec->ids[index], as->id);
507 tegra_smmu_disable(smmu, fwspec->ids[index], as->id);
508 tegra_smmu_as_unprepare(smmu, as);
518 struct tegra_smmu_as *as = to_smmu_as(domain);
519 struct tegra_smmu *smmu = as->smmu;
526 tegra_smmu_disable(smmu, fwspec->ids[index], as->id);
527 tegra_smmu_as_unprepare(smmu, as);
531 static void tegra_smmu_set_pde(struct tegra_smmu_as *as, unsigned long iova,
535 struct tegra_smmu *smmu = as->smmu;
536 u32 *pd = page_address(as->pd);
543 dma_sync_single_range_for_device(smmu->dev, as->pd_dma, offset,
547 smmu_flush_ptc(smmu, as->pd_dma, offset);
548 smmu_flush_tlb_section(smmu, as->id, iova);
559 static u32 *tegra_smmu_pte_lookup(struct tegra_smmu_as *as, unsigned long iova,
563 struct tegra_smmu *smmu = as->smmu;
567 pt_page = as->pts[pd_index];
571 pd = page_address(as->pd);
577 static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova,
581 struct tegra_smmu *smmu = as->smmu;
583 if (!as->pts[pde]) {
600 as->pts[pde] = page;
602 tegra_smmu_set_pde(as, iova, SMMU_MK_PDE(dma, SMMU_PDE_ATTR |
607 u32 *pd = page_address(as->pd);
612 return tegra_smmu_pte_offset(as->pts[pde], iova);
615 static void tegra_smmu_pte_get_use(struct tegra_smmu_as *as, unsigned long iova)
619 as->count[pd_index]++;
622 static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova)
625 struct page *page = as->pts[pde];
631 if (--as->count[pde] == 0) {
632 struct tegra_smmu *smmu = as->smmu;
633 u32 *pd = page_address(as->pd);
636 tegra_smmu_set_pde(as, iova, 0);
640 as->pts[pde] = NULL;
644 static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova,
647 struct tegra_smmu *smmu = as->smmu;
655 smmu_flush_tlb_group(smmu, as->id, iova);
659 static struct page *as_get_pde_page(struct tegra_smmu_as *as,
664 struct page *page = as->pts[pde];
676 spin_unlock_irqrestore(&as->lock, *flags);
681 spin_lock_irqsave(&as->lock, *flags);
688 if (as->pts[pde]) {
692 page = as->pts[pde];
703 struct tegra_smmu_as *as = to_smmu_as(domain);
709 page = as_get_pde_page(as, iova, gfp, flags);
713 pte = as_get_pte(as, iova, &pte_dma, page);
719 tegra_smmu_pte_get_use(as, iova);
729 tegra_smmu_set_pte(as, iova, pte, pte_dma,
739 struct tegra_smmu_as *as = to_smmu_as(domain);
743 pte = tegra_smmu_pte_lookup(as, iova, &pte_dma);
747 tegra_smmu_set_pte(as, iova, pte, pte_dma, 0);
748 tegra_smmu_pte_put_use(as, iova);
756 struct tegra_smmu_as *as = to_smmu_as(domain);
760 spin_lock_irqsave(&as->lock, flags);
762 spin_unlock_irqrestore(&as->lock, flags);
770 struct tegra_smmu_as *as = to_smmu_as(domain);
773 spin_lock_irqsave(&as->lock, flags);
775 spin_unlock_irqrestore(&as->lock, flags);
783 struct tegra_smmu_as *as = to_smmu_as(domain);
788 pte = tegra_smmu_pte_lookup(as, iova, &pte_dma);
792 pfn = *pte & as->smmu->pfn_mask;
955 * the SMMU parent device is the same as the MC, so the reference count