Lines Matching refs:iommu_write_reg
115 iommu_write_reg(obj, p[i], i * sizeof(u32));
141 iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
143 iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
151 iommu_write_reg(obj, l, MMU_CNTL);
169 iommu_write_reg(obj, pa, MMU_TTB);
174 iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG);
186 iommu_write_reg(obj, l, MMU_CNTL);
245 iommu_write_reg(obj, status, MMU_IRQSTATUS);
267 iommu_write_reg(obj, val, MMU_LOCK);
278 iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM);
279 iommu_write_reg(obj, cr->ram, MMU_RAM);
281 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
282 iommu_write_reg(obj, 1, MMU_LD_TLB);
428 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY);
452 iommu_write_reg(obj, 1, MMU_GFLUSH);
823 iommu_write_reg(obj, 0, MMU_IRQENABLE);