Lines Matching refs:data
116 struct mtk_iommu_v1_data *data;
121 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
123 return component_bind_all(dev, &data->larb_imu);
128 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
130 component_unbind_all(dev, &data->larb_imu);
161 static void mtk_iommu_v1_tlb_flush_all(struct mtk_iommu_v1_data *data)
164 data->base + REG_MMU_INV_SEL);
165 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE);
169 static void mtk_iommu_v1_tlb_flush_range(struct mtk_iommu_v1_data *data,
176 data->base + REG_MMU_INV_SEL);
178 data->base + REG_MMU_INVLD_START_A);
180 data->base + REG_MMU_INVLD_END_A);
181 writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE);
183 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE,
186 dev_warn(data->dev,
188 mtk_iommu_v1_tlb_flush_all(data);
191 writel_relaxed(0, data->base + REG_MMU_CPE_DONE);
196 struct mtk_iommu_v1_data *data = dev_id;
197 struct mtk_iommu_v1_domain *dom = data->m4u_dom;
202 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST);
203 fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA);
206 fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA);
207 regval = readl_relaxed(data->base + REG_MMU_INT_ID);
215 if (report_iommu_fault(&dom->domain, data->dev, fault_iova,
217 dev_err_ratelimited(data->dev,
223 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL);
225 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
227 mtk_iommu_v1_tlb_flush_all(data);
232 static void mtk_iommu_v1_config(struct mtk_iommu_v1_data *data,
243 larb_mmu = &data->larb_imu[larbid];
255 static int mtk_iommu_v1_domain_finalise(struct mtk_iommu_v1_data *data)
257 struct mtk_iommu_v1_domain *dom = data->m4u_dom;
261 dom->pgt_va = dma_alloc_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
266 writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR);
268 dom->data = data;
290 struct mtk_iommu_v1_data *data = dom->data;
292 dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE,
299 struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev);
305 mtk_mapping = data->mapping;
309 if (!data->m4u_dom) {
310 data->m4u_dom = dom;
311 ret = mtk_iommu_v1_domain_finalise(data);
313 data->m4u_dom = NULL;
318 mtk_iommu_v1_config(data, dev, true);
324 struct mtk_iommu_v1_data *data = dev_iommu_priv_get(dev);
326 mtk_iommu_v1_config(data, dev, false);
350 mtk_iommu_v1_tlb_flush_range(dom->data, iova, *mapped);
368 mtk_iommu_v1_tlb_flush_range(dom->data, iova, size);
396 struct mtk_iommu_v1_data *data;
429 data = dev_iommu_priv_get(dev);
430 mtk_mapping = data->mapping;
438 data->mapping = mtk_mapping;
453 struct mtk_iommu_v1_data *data;
484 data = dev_iommu_priv_get(dev);
500 larbdev = data->larb_imu[larbid].dev;
509 return &data->iommu;
515 struct mtk_iommu_v1_data *data;
518 data = dev_iommu_priv_get(dev);
519 mtk_mapping = data->mapping;
529 struct mtk_iommu_v1_data *data;
533 data = dev_iommu_priv_get(dev);
535 larbdev = data->larb_imu[larbid].dev;
539 static int mtk_iommu_v1_hw_init(const struct mtk_iommu_v1_data *data)
544 ret = clk_prepare_enable(data->bclk);
546 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret);
551 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
561 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL);
564 writel_relaxed(data->protect_base,
565 data->base + REG_MMU_IVRP_PADDR);
567 writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM);
569 if (devm_request_irq(data->dev, data->irq, mtk_iommu_v1_isr, 0,
570 dev_name(data->dev), (void *)data)) {
571 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
572 clk_disable_unprepare(data->bclk);
573 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq);
612 struct mtk_iommu_v1_data *data;
618 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
619 if (!data)
622 data->dev = dev;
629 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
632 data->base = devm_ioremap_resource(dev, res);
633 if (IS_ERR(data->base))
634 return PTR_ERR(data->base);
636 data->irq = platform_get_irq(pdev, 0);
637 if (data->irq < 0)
638 return data->irq;
640 data->bclk = devm_clk_get(dev, "bclk");
641 if (IS_ERR(data->bclk))
642 return PTR_ERR(data->bclk);
671 data->larb_imu[i].dev = &plarbdev->dev;
677 platform_set_drvdata(pdev, data);
679 ret = mtk_iommu_v1_hw_init(data);
683 ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL,
688 ret = iommu_device_register(&data->iommu, &mtk_iommu_v1_ops, dev);
698 iommu_device_unregister(&data->iommu);
700 iommu_device_sysfs_remove(&data->iommu);
702 clk_disable_unprepare(data->bclk);
708 struct mtk_iommu_v1_data *data = platform_get_drvdata(pdev);
710 iommu_device_sysfs_remove(&data->iommu);
711 iommu_device_unregister(&data->iommu);
713 clk_disable_unprepare(data->bclk);
714 devm_free_irq(&pdev->dev, data->irq, data);
720 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
721 struct mtk_iommu_v1_suspend_reg *reg = &data->reg;
722 void __iomem *base = data->base;
734 struct mtk_iommu_v1_data *data = dev_get_drvdata(dev);
735 struct mtk_iommu_v1_suspend_reg *reg = &data->reg;
736 void __iomem *base = data->base;
738 writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR);
744 writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR);